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Message-ID: <CANAwSgR1+Fb5Si6yBU6JXCfRiq-XU0xjr-ecVbnALMj7qmv0Sg@mail.gmail.com>
Date: Tue, 27 Feb 2024 18:34:05 +0530
From: Anand Moon <linux.amoon@...il.com>
To: neil.armstrong@...aro.org
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Kevin Hilman <khilman@...libre.com>, Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the
Amlogic S922X SoC
Hi Niel,
On Tue, 6 Feb 2024 at 20:31, <neil.armstrong@...aro.org> wrote:
>
> On 06/02/2024 11:15, Anand Moon wrote:
> > Hi Neil,
> >
> > On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@...aro.org> wrote:
> >>
> >> On 05/02/2024 18:19, Anand Moon wrote:
> >>> As per S922X datasheet add missing cache information to the Amlogic
> >>> S922X SoC.
> >>>
> >>> - Each Cortex-A53 core has 32 KB of instruction cache and
> >>> 32 KB of L1 data cache available.
> >>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> >>> 64 KB of L1 data cache available.
> >>> - The little (A53) cluster has 512 KB of unified L2 cache available.
> >>> - The big (A73) cluster has 1 MB of unified L2 cache available.
> >>
> >> Datasheet says:
> >> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
> >> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
> >>
> > Ok,
> >
> > Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
> > the architecture with some improvements in cache features
> > hence I update the changes accordingly.
> > Also, I checked this in the ARM documentation earlier on this.
>
> I don't understand, Amlogic states it's a shared L2 cache, but you trust
> the ARM documentation instead ???
Yes please find the Cortex™-A73 TRM
L1 Cache
https://developer.arm.com/documentation/100048/0002/level-1-memory-system/about-the-l1-memory-system?lang=en
L2 Cache
https://developer.arm.com/documentation/100048/0002/level-2-memory-system/about-the-l2-memory-system?lang=en
>
> >
> >> And there's no indication of the L1 or L2 cache sizes.
> >
> > What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
> > L1 and L2 cache size since it is part of the core features.
> > but I opted for these size values from a Wikipedia article.
> >
> > On my Odroid N2+, I observe the following.
> >
> > I have also done some testing on the stress-ng to verify this.
>
>
> Ok I don't feel confident adding numbers that comes out of thin air,
> and even more since they are only shared to userspace.
>
> I think we should only add the numbers which are 100% sure
Best way to let the Amlogic SoC members comment on the CPU L1/ / L2 cache size.
But with the lack of pref PMU events we cannot test this feature.
>
>
> This looks pretty, but let's keep exporting verified data.
>
This CPU hardware supports cache this feature, but with missing PMU for this cpu
so its not getting listed hardware events like cache-misses cache-references
alarm@...hl-on2:~$ sudo perf list
[sudo] password for alarm:
List of pre-defined events (to be used in -e or -M):
alignment-faults [Software event]
bpf-output [Software event]
cgroup-switches [Software event]
context-switches OR cs [Software event]
cpu-clock [Software event]
cpu-migrations OR migrations [Software event]
dummy [Software event]
emulation-faults [Software event]
major-faults [Software event]
minor-faults [Software event]
page-faults OR faults [Software event]
task-clock [Software event]
duration_time [Tool event]
user_time [Tool event]
system_time [Tool event]
meson_ddr_bw/chan_1_rw_bytes/ [Kernel PMU event]
meson_ddr_bw/chan_2_rw_bytes/ [Kernel PMU event]
meson_ddr_bw/chan_3_rw_bytes/ [Kernel PMU event]
meson_ddr_bw/chan_4_rw_bytes/ [Kernel PMU event]
meson_ddr_bw/total_rw_bytes/ [Kernel PMU event]
rNNN [Raw hardware
event descriptor]
cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware
event descriptor]
[(see 'man perf-list' on how to encode it)]
mem:<addr>[/len][:access] [Hardware breakpoint]
alarmtimer:alarmtimer_cancel [Tracepoint event]
alarmtimer:alarmtimer_fired [Tracepoint event]
alarmtimer:alarmtimer_start [Tracepoint event]
alarmtimer:alarmtimer_suspend [Tracepoint event]
asoc:snd_soc_bias_level_done [Tracepoint event]
asoc:snd_soc_bias_level_start [Tracepoint event]
asoc:snd_soc_dapm_connected [Tracepoint event]
asoc:snd_soc_dapm_done [Tracepoint event]
asoc:snd_soc_dapm_path [Tracepoint event]
asoc:snd_soc_dapm_start [Tracepoint event]
asoc:snd_soc_dapm_walk_done [Tracepoint event]
asoc:snd_soc_dapm_widget_event_done [Tracepoint event]
asoc:snd_soc_dapm_widget_event_start [Tracepoint event]
asoc:snd_soc_dapm_widget_power [Tracepoint event]
asoc:snd_soc_jack_irq [Tracepoint event]
asoc:snd_soc_jack_notify [Tracepoint event]
asoc:snd_soc_jack_report [Tracepoint event]
binder:binder_alloc_lru_end [Tracepoint event]
binder:binder_alloc_lru_start [Tracepoint event]
binder:binder_alloc_page_end [Tracepoint event]
binder:binder_alloc_page_start [Tracepoint event]
binder:binder_command [Tracepoint event]
binder:binder_free_lru_end [Tracepoint event]
binder:binder_free_lru_start [Tracepoint event]
binder:binder_ioctl [Tracepoint event]
binder:binder_ioctl_done [Tracepoint event]
binder:binder_lock [Tracepoint event]
binder:binder_locked [Tracepoint event]
binder:binder_read_done [Tracepoint event]
binder:binder_return [Tracepoint event]
binder:binder_transaction [Tracepoint event]
binder:binder_transaction_alloc_buf [Tracepoint event]
binder:binder_transaction_buffer_release [Tracepoint event]
binder:binder_transaction_failed_buffer_release [Tracepoint event]
binder:binder_transaction_fd_recv [Tracepoint event]
[root@...hl-on2 alarm]# perf stat -B -e
cache-references,cache-misses,cycles,instructions,branches,faults,migrations
sleep 5
Performance counter stats for 'sleep 5':
<not supported> cache-references
<not supported> cache-misses
<not supported> cycles
<not supported> instructions
<not supported> branches
56 faults
0 migrations
5.003404106 seconds time elapsed
0.003396000 seconds user
0.000000000 seconds sys
Thanks
-Anand
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