linux-kernel - Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC

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Message-ID: <CANAwSgQvYyE3rZqBHR2_Q0FzggznOh=fhtBQVJZ1DRn73P24pQ@mail.gmail.com>
Date: Wed, 20 Aug 2025 19:30:38 +0530
From: Anand Moon <linux.amoon@...il.com>
To: neil.armstrong@...aro.org
Cc: Rob Herring <robh+dt@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Kevin Hilman <khilman@...libre.com>, Jerome Brunet <jbrunet@...libre.com>, 
	Martin Blumenstingl <martin.blumenstingl@...glemail.com>, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the
 Amlogic S922X SoC

Hi Neil,

On Tue, 27 Feb 2024 at 18:34, Anand Moon <linux.amoon@...il.com> wrote:
>
> Hi Niel,
>
> On Tue, 6 Feb 2024 at 20:31, <neil.armstrong@...aro.org> wrote:
> >
> > On 06/02/2024 11:15, Anand Moon wrote:
> > > Hi Neil,
> > >
> > > On Tue, 6 Feb 2024 at 14:30, Neil Armstrong <neil.armstrong@...aro.org> wrote:
> > >>
> > >> On 05/02/2024 18:19, Anand Moon wrote:
> > >>> As per S922X datasheet add missing cache information to the Amlogic
> > >>> S922X SoC.
> > >>>
> > >>> - Each Cortex-A53 core has 32 KB of instruction cache and
> > >>>        32 KB of L1 data cache available.
> > >>> - Each Cortex-A73 core has 64 KB of L1 instruction cache and
> > >>>        64 KB of L1 data cache available.
> > >>> - The little (A53) cluster has 512 KB of unified L2 cache available.
> > >>> - The big (A73) cluster has 1 MB of unified L2 cache available.
> > >>
> > >> Datasheet says:
> > >> The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each
> > >> core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53
> > >>
> > > Ok,
> > >
> > > Since all the Cortex™-A73 and Cortex™-A53 share some improvements in
> > > the architecture with some improvements in cache features
> > > hence I update the changes accordingly.
> > > Also, I checked this in the ARM documentation earlier on this.
> >
> > I don't understand, Amlogic states it's a shared L2 cache, but you trust
> > the ARM documentation instead ???
>
> Yes please find the Cortex™-A73 TRM
> L1 Cache
> https://developer.arm.com/documentation/100048/0002/level-1-memory-system/about-the-l1-memory-system?lang=en
> L2 Cache
> https://developer.arm.com/documentation/100048/0002/level-2-memory-system/about-the-l2-memory-system?lang=en
> >
> > >
> > >> And there's no indication of the L1 or L2 cache sizes.
> > >
> > > What I feel is in general all the Cortex™-A73 and Cortex™-A53 supports
> > > L1 and L2 cache size since it is part of the core features.
> > > but I opted for these size values from a Wikipedia article.
> > >
> > > On my Odroid N2+, I observe the following.
> > >
> > > I have also done some testing on the stress-ng to verify this.
> >
> >
> > Ok I don't feel confident adding numbers that comes out of thin air,
> > and even more since they are only shared to userspace.
> >
> > I think we should only add the numbers which are 100% sure
>
> Best way to let the Amlogic SoC members comment on the CPU  L1/ / L2 cache size.
> But with the lack of pref PMU events we cannot test this feature.
>
> >
> >
> > This looks pretty, but let's keep exporting verified data.
> >
I just wanted to revisit this patch series with some updates on

Here is where the Android TV provides the cache details.
[1] https://androidpctv.com/comparative-amlogic-s922x/

Amlogic S922X Hexa Core SoC has four ARM Cortex-A73 cores capable of
reaching 1.8Ghz
with 1MB L2 cache + 2 Cortex-A53 RAM processors with 256k L2 cache,

https://boardor.com/blog/understanding-the-architecture-of-arm-cortex-a53-cache

Also  Amlogic A311D processor utilizes a "big.LITTLE" architecture, combining:

Quad-core ARM Cortex-A73:
Each Cortex-A73 core has:
     64 KB L1 instruction cache 64 KB L1 data cache
The Cortex-A73 cluster shares a 1 MB unified L2 cache.

Dual-core ARM Cortex-A53:
Each Cortex-A53 core has:
  32 KB L1 instruction cache, 32 KB L1 data cache

The Cortex-A53 cluster shares a 512 KB unified L2 cache.

>From what I understand, CPU caches are a core feature of the CPU.
Do you think I should update these patches and resend ?

Thanks
-Anand