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Message-ID: <20240228-rarity-underuse-4ea0ceaa9688@spud>
Date: Wed, 28 Feb 2024 10:13:52 +0000
From: Conor Dooley <conor@...nel.org>
To: Samuel Holland <samuel.holland@...ive.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Andrew Jones <ajones@...tanamicro.com>,
linux-kernel@...r.kernel.org, Alexandre Ghiti <alex@...ti.fr>,
linux-riscv@...ts.infradead.org,
Stefan O'Rear <sorear@...tmail.com>, stable@...r.kernel.org
Subject: Re: [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running
in M-mode
On Tue, Feb 27, 2024 at 10:55:33PM -0800, Samuel Holland wrote:
> When the kernel is running in M-mode, the CBZE bit must be set in the
> menvcfg CSR, not in senvcfg.
>
> Cc: <stable@...r.kernel.org>
> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
> Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Cheers,
Conor.
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