lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240228145051.GA271533@bhelgaas>
Date: Wed, 28 Feb 2024 08:50:51 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konrad.dybcio@...aro.org>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof WilczyƄski <kw@...ux.com>,
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Johan Hovold <johan+linaro@...nel.org>,
	Brian Masney <bmasney@...hat.com>,
	Georgi Djakov <djakov@...nel.org>, linux-arm-msm@...r.kernel.org,
	linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, vireshk@...nel.org,
	quic_vbadigan@...cinc.com, quic_skananth@...cinc.com,
	quic_nitegupt@...cinc.com, quic_parass@...cinc.com,
	Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Subject: Re: [PATCH v7 3/7] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe
 path

On Wed, Feb 28, 2024 at 12:08:37PM +0530, Krishna Chaitanya Chundru wrote:
> On 2/28/2024 4:52 AM, Bjorn Helgaas wrote:
> > On Fri, Feb 23, 2024 at 08:18:00PM +0530, Krishna chaitanya chundru wrote:
> > > To access PCIe registers, PCIe BAR space, config space the CPU-PCIe
> > > ICC(interconnect consumers) path should be voted otherwise it may
> > > lead to NoC(Network on chip) timeout. We are surviving because of
> > > other driver vote for this path.
> > > As there is less access on this path compared to PCIe to mem path
> > > add minimum vote i.e 1KBps bandwidth always.

> > > +	 * The config space, BAR space and registers goes through cpu-pcie path.
> > > +	 * Set peak bandwidth to 1KBps as recommended by HW team for this path all the time.
> > 
> > Wrap to fit in 80 columns.

> We have limit up to 100 columns in the driver right, I am ok to change to 80
> but just checking if I misunderstood something.

I should have said "wrap to fit in 80 columns to match the rest of the
file."  I looked at pcie-qcom.c, and with a few minor exceptions, it
fits in 80 columns, and maintaining that consistency makes it easier
to browse.  Sometimes exceptions make sense for code, but for
comments, having some that fit in 80 columns and some that require 100
just makes life harder.

Bjorn

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ