linux-kernel - RE: [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for HDMA platforms

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Message-ID:
 <TYCPR01MB11040F44BB95F0483EFC8DF0CD8272@TYCPR01MB11040.jpnprd01.prod.outlook.com>
Date: Fri, 8 Mar 2024 11:42:54 +0000
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Jingoo Han
	<jingoohan1@...il.com>, Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>, Rob Herring
	<robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Marek Vasut
	<marek.vasut+renesas@...il.com>, Kishon Vijay Abraham I <kishon@...nel.org>
CC: Serge Semin <fancer.lancer@...il.com>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-renesas-soc@...r.kernel.org"
	<linux-renesas-soc@...r.kernel.org>, "linux-arm-msm@...r.kernel.org"
	<linux-arm-msm@...r.kernel.org>, "mhi@...ts.linux.dev" <mhi@...ts.linux.dev>,
	Siddharth Vadapalli <s-vadapalli@...com>, Frank Li <Frank.Li@....com>
Subject: RE: [PATCH v4 2/5] PCI: dwc: Skip finding eDMA channels count for
 HDMA platforms

> From: Manivannan Sadhasivam, Sent: Wednesday, March 6, 2024 7:22 PM
> 
> In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way
> the drivers can auto detect the number of read/write channels as like its
> predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA
> have to pass the channels count during probe.
> 
> To accommodate that, let's skip the existing auto detection of channels
> count procedure for HDMA based platforms. If the channels count passed by
> the glue drivers were wrong in any form, then the existing sanity check
> will catch it.
> 
> Suggested-by: Serge Semin <fancer.lancer@...il.com>
> Reviewed-by: Siddharth Vadapalli <s-vadapalli@...com>
> Reviewed-by: Frank Li <Frank.Li@....com>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>

Best regards,
Yoshihiro Shimoda

> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 3a26dfc5368f..599991b7ffb2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -927,13 +927,18 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci)
>  {
>  	u32 val;
> 
> -	if (pci->edma.mf == EDMA_MF_EDMA_LEGACY)
> -		val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> -	else
> +	/*
> +	 * Autodetect the read/write channels count only for non-HDMA platforms.
> +	 * HDMA platforms doesn't support autodetect, so the glue drivers should've
> +	 * passed the valid count already. If not, the below sanity check will
> +	 * catch it.
> +	 */
> +	if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) {
>  		val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
> 
> -	pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
> -	pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
> +		pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
> +		pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
> +	}
> 
>  	/* Sanity check the channels count if the mapping was incorrect */
>  	if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH ||
> 
> --
> 2.25.1