linux-kernel - Re: [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

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Date: Fri, 08 Mar 2024 18:15:12 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Chen Wang <unicornxw@...il.com>, aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org, devicetree@...r.kernel.org, guoren@...nel.org, haijiao.liu@...hgo.com, inochiama@...look.com, jszhang@...nel.org, krzysztof.kozlowski+dt@...aro.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, mturquette@...libre.com, palmer@...belt.com, paul.walmsley@...ive.com, richardcochran@...il.com, robh+dt@...nel.org, samuel.holland@...ive.com, xiaoguang.xing@...hgo.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: Re: [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

Quoting Chen Wang (2024-02-19 19:08:59)
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clock-controller@...00000 {

This is the same address as the pll binding before this. How does that
work? It's the same register area as the pll node. The resulting DTB
should only have one compatible for this node.

> +      compatible = "sophgo,sg2042-rpgate";
> +      reg = <0x10000000 0x10000>;
> +      clocks = <&clkgen 85>;
> +      #clock-cells = <1>;
> +    };