linux-kernel - Re: [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

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Date: Sun, 10 Mar 2024 09:28:21 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Stephen Boyd <sboyd@...nel.org>, Chen Wang <unicornxw@...il.com>,
 aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
 devicetree@...r.kernel.org, guoren@...nel.org, haijiao.liu@...hgo.com,
 inochiama@...look.com, jszhang@...nel.org,
 krzysztof.kozlowski+dt@...aro.org, linux-clk@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
 mturquette@...libre.com, palmer@...belt.com, paul.walmsley@...ive.com,
 richardcochran@...il.com, robh+dt@...nel.org, samuel.holland@...ive.com,
 xiaoguang.xing@...hgo.com
Subject: Re: [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks
 for SG2042


On 2024/3/9 10:15, Stephen Boyd wrote:
> Quoting Chen Wang (2024-02-19 19:08:59)
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    clock-controller@...00000 {
> This is the same address as the pll binding before this. How does that
> work? It's the same register area as the pll node. The resulting DTB
> should only have one compatible for this node.

Hi, Stephen,

This is just examples in bindings file, it should be no problem. The 
resulting DTS/DTB will have different addresses.

And I see you mentined you have alreay applied this binding to clk-next 
in another email. right?

Thanks,

Chen

>
>> +      compatible = "sophgo,sg2042-rpgate";
>> +      reg = <0x10000000 0x10000>;
>> +      clocks = <&clkgen 85>;
>> +      #clock-cells = <1>;
>> +    };