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Message-ID: <f9cc5817-234e-4612-acbb-29977e0da760@sifive.com>
Date: Tue, 12 Mar 2024 12:40:09 -0500
From: Samuel Holland <samuel.holland@...ive.com>
To: Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>, Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu>
Cc: atishp@...osinc.com, Anup Patel <apatel@...tanamicro.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Ley Foon Tan <lftan.linux@...il.com>, stable@...r.kernel.org
Subject: Re: [PATCH v3] clocksource: timer-riscv: Clear timer interrupt on
timer initialization
On 2024-03-06 11:23 AM, Ley Foon Tan wrote:
> In the RISC-V specification, the stimecmp register doesn't have a default
> value. To prevent the timer interrupt from being triggered during timer
> initialization, clear the timer interrupt by writing stimecmp with a
> maximum value.
>
> Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available")
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>
>
> ---
> v3:
> Resolved comment from Samuel Holland.
> - Function riscv_clock_event_stop() needs to be called before
> clockevents_config_and_register(), move riscv_clock_event_stop().
>
> v2:
> Resolved comments from Anup.
> - Moved riscv_clock_event_stop() to riscv_timer_starting_cpu().
> - Added Fixes tag
> ---
> drivers/clocksource/timer-riscv.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
Tested-by: Samuel Holland <samuel.holland@...ive.com>
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