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Message-ID: <20240320071527.13443-4-quic_schintav@quicinc.com>
Date: Wed, 20 Mar 2024 00:14:47 -0700
From: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
To: <agross@...nel.org>, <andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<mani@...nel.org>
CC: <quic_msarkar@...cinc.com>, <quic_kraravin@...cinc.com>,
Lorenzo Pieralisi
<lpieralisi@...nel.org>,
Krzysztof Wilczyński
<kw@...ux.com>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas
<bhelgaas@...gle.com>,
Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel
<gustavo.pimentel@...opsys.com>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
Serge Semin <fancer.lancer@...il.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Conor Dooley
<conor.dooley@...rochip.com>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>
Subject: [PATCH v2 3/3] PCI: qcom: Add rx margining settings for gen4
Add rx margining settings for gen4 operation.
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 23 +++++++++++++
drivers/pci/controller/dwc/pcie-qcom-cmn.c | 35 ++++++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom-cmn.h | 11 +++++-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++-
drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-
5 files changed, 74 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 064744bfe35a..ce1c5f9c406a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -206,6 +206,29 @@
#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
+/*
+ * GEN4 lane margining register definitions
+ */
+#define GEN4_LANE_MARGINING_1_OFF 0xb80
+#define MARGINING_MAX_VOLTAGE_OFFSET_MASK GENMASK(29, 24)
+#define MARGINING_NUM_VOLTAGE_STEPS_MASK GENMASK(22, 16)
+#define MARGINING_MAX_TIMING_OFFSET_MASK GENMASK(13, 8)
+#define MARGINING_NUM_TIMING_STEPS_MASK GENMASK(5, 0)
+#define MARGINING_MAX_VOLTAGE_OFFSET_SHIFT 24
+#define MARGINING_NUM_VOLTAGE_STEPS_SHIFT 16
+#define MARGINING_MAX_TIMING_OFFSET_SHIFT 8
+
+#define GEN4_LANE_MARGINING_2_OFF 0xb84
+#define MARGINING_IND_ERROR_SAMPLER BIT(28)
+#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27)
+#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26)
+#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25)
+#define MARGINING_VOLTAGE_SUPPORTED BIT(24)
+#define MARGINING_MAXLANES_MASK GENMASK(20, 16)
+#define MARGINING_SAMPLE_RATE_TIMING_MASK GENMASK(13, 8)
+#define MARGINING_SAMPLE_RATE_VOLTAGE_MASK GENMASK(5, 0)
+#define MARGINING_MAXLANES_SHIFT 16
+#define MARGINING_SAMPLE_RATE_TIMING_SHIFT 8
/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
diff --git a/drivers/pci/controller/dwc/pcie-qcom-cmn.c b/drivers/pci/controller/dwc/pcie-qcom-cmn.c
index 208a55e8e9a1..bf6b27ee8327 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-cmn.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-cmn.c
@@ -53,6 +53,41 @@ void qcom_pcie_cmn_set_16gt_eq_settings(struct dw_pcie *pci)
}
EXPORT_SYMBOL_GPL(qcom_pcie_cmn_set_16gt_eq_settings);
+void qcom_pcie_cmn_set_16gt_rx_margining_settings(struct dw_pcie *pci)
+{
+ u32 reg;
+
+ reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
+ reg &= ~MARGINING_MAX_VOLTAGE_OFFSET_MASK;
+ reg |= (MARGINING_MAX_VOLTAGE_OFFSET_VAL <<
+ MARGINING_MAX_VOLTAGE_OFFSET_SHIFT);
+ reg &= ~MARGINING_NUM_VOLTAGE_STEPS_MASK;
+ reg |= (MARGINING_NUM_VOLTAGE_STEPS_VAL <<
+ MARGINING_NUM_VOLTAGE_STEPS_SHIFT);
+ reg &= ~MARGINING_MAX_TIMING_OFFSET_MASK;
+ reg |= (MARGINING_MAX_TIMING_OFFSET_VAL <<
+ MARGINING_MAX_TIMING_OFFSET_SHIFT);
+ reg &= ~MARGINING_NUM_TIMING_STEPS_MASK;
+ reg |= MARGINING_NUM_TIMING_STEPS_VAL;
+ dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
+
+ reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
+ reg |= MARGINING_IND_ERROR_SAMPLER;
+ reg |= MARGINING_SAMPLE_REPORTING_METHOD;
+ reg |= MARGINING_IND_LEFT_RIGHT_TIMING;
+ reg |= MARGINING_VOLTAGE_SUPPORTED;
+ reg &= ~MARGINING_IND_UP_DOWN_VOLTAGE;
+ reg &= ~MARGINING_MAXLANES_MASK;
+ reg |= (pci->num_lanes <<
+ MARGINING_MAXLANES_SHIFT);
+ reg &= ~MARGINING_SAMPLE_RATE_TIMING_MASK;
+ reg |= (MARGINING_SAMPLE_RATE_TIMING_VAL <<
+ MARGINING_SAMPLE_RATE_TIMING_SHIFT);
+ reg |= MARGINING_SAMPLE_RATE_VOLTAGE_VAL;
+ dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
+}
+EXPORT_SYMBOL_GPL(qcom_pcie_cmn_set_16gt_rx_margining_settings);
+
int qcom_pcie_cmn_icc_get_resource(struct dw_pcie *pci, struct icc_path *icc_mem)
{
if (IS_ERR(pci))
diff --git a/drivers/pci/controller/dwc/pcie-qcom-cmn.h b/drivers/pci/controller/dwc/pcie-qcom-cmn.h
index 97302e8fafa8..11d6b00372ec 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-cmn.h
+++ b/drivers/pci/controller/dwc/pcie-qcom-cmn.h
@@ -11,9 +11,18 @@
#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_16GT_VAL 0x5
#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_16GT_VAL 0x5
-#define GEN3_EQ_FMDC_N_EVALS_16GT_VAL 0xD
+#define GEN3_EQ_FMDC_N_EVALS_16GT_VAL 0xD
+
+/* GEN4(16GT/s) RX margining settings */
+#define MARGINING_MAX_VOLTAGE_OFFSET_VAL 0x24
+#define MARGINING_NUM_VOLTAGE_STEPS_VAL 0x78
+#define MARGINING_MAX_TIMING_OFFSET_VAL 0x32
+#define MARGINING_NUM_TIMING_STEPS_VAL 0x10
+#define MARGINING_SAMPLE_RATE_TIMING_VAL 0x3f
+#define MARGINING_SAMPLE_RATE_VOLTAGE_VAL 0x3f
int qcom_pcie_cmn_icc_get_resource(struct dw_pcie *pci, struct icc_path *icc_mem);
int qcom_pcie_cmn_icc_init(struct dw_pcie *pci, struct icc_path *icc_mem);
void qcom_pcie_cmn_icc_update(struct dw_pcie *pci, struct icc_path *icc_mem);
void qcom_pcie_cmn_set_16gt_eq_settings(struct dw_pcie *pci);
+void qcom_pcie_cmn_set_16gt_rx_margining_settings(struct dw_pcie *pci);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index b6bcab21bb9f..b4d53f96eb9e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -438,8 +438,10 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
goto err_disable_resources;
}
- if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT)
+ if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) {
qcom_pcie_cmn_set_16gt_eq_settings(pci);
+ qcom_pcie_cmn_set_16gt_rx_margining_settings(pci);
+ }
/*
* The physical address of the MMIO region which is exposed as the BAR
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index b0a22a000fa3..3dfb4d165ba5 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -263,8 +263,10 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
{
struct qcom_pcie *pcie = to_qcom_pcie(pci);
- if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT)
+ if (pcie_link_speed[pci->link_gen] == PCIE_SPEED_16_0GT) {
qcom_pcie_cmn_set_16gt_eq_settings(pci);
+ qcom_pcie_cmn_set_16gt_rx_margining_settings(pci);
+ }
/* Enable Link Training state machine */
if (pcie->cfg->ops->ltssm_enable)
--
2.43.2
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