linux-kernel - Re: [PATCH v3 4/4] arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3

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Message-ID: <4f5a91e7-7d67-4012-9928-90d8fbfea582@linaro.org>
Date: Thu, 21 Mar 2024 18:54:47 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Wadim Mueller <wafgo01@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Ulf Hansson <ulf.hansson@...aro.org>,
 Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>,
 Pengutronix Kernel Team <kernel@...gutronix.de>,
 Fabio Estevam <festevam@...il.com>, NXP Linux Team <linux-imx@....com>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Jiri Slaby <jirislaby@...nel.org>, Chester Lin <chester62515@...il.com>,
 Andreas Färber <afaerber@...e.de>,
 Matthias Brugger <mbrugger@...e.com>, NXP S32 Linux Team <s32@....com>,
 Tim Harvey <tharvey@...eworks.com>,
 Alexander Stein <alexander.stein@...tq-group.com>,
 Gregor Herburger <gregor.herburger@...tq-group.com>,
 Marek Vasut <marex@...x.de>, Hugo Villeneuve <hvilleneuve@...onoff.com>,
 Marco Felsch <m.felsch@...gutronix.de>,
 Markus Niebel <Markus.Niebel@...tq-group.com>,
 Matthias Schiffer <matthias.schiffer@...group.com>,
 Stefan Wahren <stefan.wahren@...rgebyte.com>,
 Bjorn Helgaas <bhelgaas@...gle.com>,
 Philippe Schenker <philippe.schenker@...adex.com>,
 Li Yang <leoyang.li@....com>, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v3 4/4] arm64: dts: S32G3: Introduce device tree for
 S32G-VNP-RDB3

On 21/03/2024 16:41, Wadim Mueller wrote:
> This commit adds device tree support for the NXP S32G3-based
> S32G-VNP-RDB3 Board [1].
> 
> The S32G3 features an 8-core ARM Cortex-A53 based SoC developed by NXP.

..

> +
> +		cpu7: cpu@103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x103>;
> +			enable-method = "psci";
> +			clocks = <&dfs 0>;
> +		};
> +	};
> +
> +	pmu {

Please order things alphabetically. See DTS coding style.

> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
> +			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
> +		arm,no-tick-in-suspend;
> +	};
> +
> +	reserved-memory  {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		scmi_shmem: shm@...00000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0xd0000000 0x0 0x80>;
> +			no-map;
> +		};
> +	};
> +
> +	firmware {
> +		scmi: scmi {
> +			compatible = "arm,scmi-smc";
> +			shmem = <&scmi_shmem>;
> +			arm,smc-id = <0xc20000fe>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			dfs: protocol@13 {
> +				reg = <0x13>;
> +				#clock-cells = <1>;
> +			};
> +
> +			clks: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +
> +		psci: psci {
> +			compatible = "arm,psci-1.0";
> +			method = "smc";
> +		};
> +	};
> +
> +	soc@0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0x80000000>;
> +
> +		uart0: serial@...c8000 {
> +			compatible = "nxp,s32g3-linflexuart",
> +				     "fsl,s32v234-linflexuart";
> +			reg = <0x401c8000 0x3000>;
> +			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@...cc000 {
> +			compatible = "nxp,s32g3-linflexuart",
> +				     "fsl,s32v234-linflexuart";
> +			reg = <0x401cc000 0x3000>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@...bc000 {
> +			compatible = "nxp,s32g3-linflexuart",
> +				     "fsl,s32v234-linflexuart";
> +			reg = <0x402bc000 0x3000>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
> +			status = "disabled";
> +		};
> +
> +		gic: interrupt-controller@...00000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			reg = <0x50800000 0x10000>,
> +			      <0x50900000 0x200000>,
> +			      <0x50400000 0x2000>,
> +			      <0x50410000 0x2000>,
> +			      <0x50420000 0x2000>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		usdhc0: mmc@...f0000 {

Keep ordered by unit address.



Best regards,
Krzysztof