linux-kernel - [tip: perf/urgent] perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later

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Message-ID: <171144085875.10875.4543656707439916020.tip-bot2@tip-bot2>
Date: Tue, 26 Mar 2024 08:14:18 -0000
From: "tip-bot2 for Sandipan Das" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Sandipan Das <sandipan.das@....com>, Ingo Molnar <mingo@...nel.org>,
 Ian Rogers <irogers@...gle.com>, x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: perf/urgent] perf/x86/amd/core: Define a proper ref-cycles
 event for Zen 4 and later

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     68cdf1e6e8f2ce78ed7d8f5d80844fd75a9c54ff
Gitweb:        https://git.kernel.org/tip/68cdf1e6e8f2ce78ed7d8f5d80844fd75a9c54ff
Author:        Sandipan Das <sandipan.das@....com>
AuthorDate:    Mon, 25 Mar 2024 13:17:54 +05:30
Committer:     Ingo Molnar <mingo@...nel.org>
CommitterDate: Tue, 26 Mar 2024 09:04:21 +01:00

perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later

Add the "ref-cycles" event for AMD processors based on Zen 4 and later
microarchitectures. The backing event is based on PMCx120 which counts
cycles not in halt state in P0 frequency (same as MPERF).

Signed-off-by: Sandipan Das <sandipan.das@....com>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
Reviewed-by: Ian Rogers <irogers@...gle.com>
Link: https://lore.kernel.org/r/089155f19f7c7e65aeb1caa727a882e2ca9b8b04.1711352180.git.sandipan.das@amd.com
---
 arch/x86/events/amd/core.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index af8add6..985ef3b 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
 	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,
 };
 
+static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
+{
+	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,
+	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
+	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,
+	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,
+	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,
+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,
+	[PERF_COUNT_HW_REF_CPU_CYCLES]		= 0x100000120,
+};
+
 static u64 amd_pmu_event_map(int hw_event)
 {
+	if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
+		return amd_zen4_perfmon_event_map[hw_event];
+
 	if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
 		return amd_zen2_perfmon_event_map[hw_event];