Message-ID:
 <NTZPR01MB0986A4F77EF371F7CBEE3A51E13BA@NTZPR01MB0986.CHNPR01.prod.partner.outlook.cn>
Date: Thu, 28 Mar 2024 07:27:05 +0000
From: Ziv Xu <ziv.xu@...rfivetech.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, Rob Herring
	<robh+dt@...nel.org>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>, Philipp Zabel <p.zabel@...gutronix.de>, Walker Chen
	<walker.chen@...rfivetech.com>, Xingyu Wu <xingyu.wu@...rfivetech.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Conor Dooley
	<conor@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, Emil Renner
 Berthing <emil.renner.berthing@...onical.com>, Christophe JAILLET
	<christophe.jaillet@...adoo.fr>
Subject:
 回复: [PATCH v9 0/3] Add timer driver for StarFive JH7110 RISC-V SoC

> This patch serises are to add timer driver for the StarFive JH7110 RISC-V SoC.
> The first patch adds documentation to describe device tree bindings. The
> subsequent patch adds timer driver and support
> JH7110 SoC. The last patch adds device node about timer in JH7110 dts.
> 
> This timer has four free-running 32 bit counters and runs in 24MHz clock on
> StarFive JH7110 SoC. And each channel(counter) triggers an interrupt when
> timeout. They support one-shot mode and continuous-run mode.
> 
> This timer is used as global timer and register clockevent for each CPU core
> after riscv-timer registration on the StarFive JH7110 SoC.
> 
> Changes since v8:
> - Rebased on 6.8
> - Improved the cpu hot swap startup process of the timer.
> - Modified irq request timing to prevent sleep.
> - Deleted clockevent suspend and resume function and these
>   operations are included in cpu hot swap operations.
> - Formated data structures.
> 
> v8:
> https://lore.kernel.org/all/20231219145402.7879-1-xingyu.wu@starfivetech.co
> m/
> 
> Changes since v7:
> - Rebased on 6.7-rc6.
> - Modified the Kconfig file and added selection in SOC_STARFIVE.
> - Used the timer as a global timer and registered as clockevent
>   for each CPU core.
> - Dropped the timeout function in the interrupt handler callback.
> - Changed the way in the functions of jh7110_timer_tick_resume() and
>   jh7110_timer_resume().
> - Dropped the registration of clocksource in the probe.
> 
> v7:
> https://lore.kernel.org/all/20231019053501.46899-1-xingyu.wu@starfivetech.c
> om/
> 
> Changes since v6:
> - Rebased on 6.6-rc6.
> - Used sizeof() instead of the numbers of characters about names.
> - Added devm_add_action_or_reset() to release the resets and
>   clocksources in the case of remove or error in the probe.
> - Added flags to check each clocksource is suceessfully registered and
>   used in the release function.
> - Dropped the variable of irq in the jh7110_clkevt struct.
> - Dropped the wrappers and used enum definitions and writel() calls
>   directly.
> 
> v6:
> https://lore.kernel.org/all/20231012081015.33121-1-xingyu.wu@starfivetech.c
> om/
> 
> Changes since v5:
> - Rebased on 6.6-rc5.
> - Changed the number about characters of name.
> - Made the clkevt->periodic to a local variable.
> - Dropped the variables of device and base.
> - Used clkevt->evt.irq directly and dropped the extra copy of irq.
> 
> V5:
> https://lore.kernel.org/all/20230907053742.250444-1-xingyu.wu@starfivetech.
> com/
> 
> Changes since v4:
> - Rebased on 6.5.
> - Dropped the useless enum and used value directly when writing
>   registers.
> - Modified the description in Kconfig.
> - Add the reviewed tag in patch 3.
> 
> v4:
> https://lore.kernel.org/all/20230814101603.166951-1-xingyu.wu@starfivetech.
> com/
> 
> Changes since v3:
> - Rebased on 6.5-rc6
> - Dropped the useless enum names like 'JH7110_TIMER_CH_0'.
> - Dropped the platform data about JH7110 and used the register offsets
>   directly.
> - Drroped the useless functions of clk_disable_unprepare().
> 
> v3:
> https://lore.kernel.org/all/20230627055313.252519-1-xingyu.wu@starfivetech.
> com/
> 
> Changes since v2:
> - Rebased on 6.4-rc7.
> - Merged the header file into the c file.
> - Renamed the functions from 'starfive_' to 'jh7110_'
> - Used function 'clocksource_register_hz' instead of
>   'clocksource_mmio_init'.
> 
> v2:
> https://lore.kernel.org/all/20230320135433.144832-1-xingyu.wu@starfivetech.
> com/
> 
> Changes since v1:
> - Added description about timer and modified properties' description
>   in dt-bindings.
> - Dropped the 'interrupt-names' and 'clock-frequency' in dt-bindings.
> - Renamed the functions and added 'starfive_'
> - Modified that the driver probe by platform bus.
> 
> v1:
> https://lore.kernel.org/all/20221223094801.181315-1-xingyu.wu@starfivetech.
> com/
> 
> Xingyu Wu (3):
>   dt-bindings: timer: Add timer for StarFive JH7110 SoC
>   clocksource: Add JH7110 timer driver
>   riscv: dts: jh7110: starfive: Add timer node
> 
>  .../bindings/timer/starfive,jh7110-timer.yaml |  96 +++++
>  MAINTAINERS                                   |   7 +
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      |  20 +
>  drivers/clocksource/Kconfig                   |  11 +
>  drivers/clocksource/Makefile                  |   1 +
>  drivers/clocksource/timer-jh7110.c            | 345 ++++++++++++++++++
>  include/linux/cpuhotplug.h                    |   1 +
>  7 files changed, 481 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>  create mode 100644 drivers/clocksource/timer-jh7110.c
> 
> --
> 2.17.1

Hi, Daniel

Could you please help to review this patch and give your comments if you have time?
Thanks.

Best Regards
Ziv Xu

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