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Message-ID: <560e9a5b236728f62be4bfd8df187071c4bffb23.camel@linaro.org>
Date: Fri, 05 Apr 2024 08:33:20 +0100
From: André Draszik <andre.draszik@...aro.org>
To: Peter Griffin <peter.griffin@...aro.org>, mturquette@...libre.com,
sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
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avri.altman@....com, bvanassche@....org, s.nawrocki@...sung.com,
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chanho61.park@...sung.com, ebiggers@...nel.org
Cc: linux-scsi@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, tudor.ambarus@...aro.org,
saravanak@...gle.com, willmcvicker@...gle.com
Subject: Re: [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg
node
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> This has some configuration bits such as sharability that
> are required by UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 38ac4fb1397e..608369cec47b 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@...00000 {
> clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> };
>
> + sysreg_hsi2: syscon@...20000 {
> + compatible = "google,gs101-hsi2-sysreg", "syscon";
> + reg = <0x14420000 0x1000>;
Should the length not be 0x10000?
Cheers,
Andre'
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