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Message-Id: <20240407123829.36474-2-cuiyunhui@bytedance.com>
Date: Sun, 7 Apr 2024 20:38:29 +0800
From: Yunhui Cui <cuiyunhui@...edance.com>
To: rafael@...nel.org,
lenb@...nel.org,
linux-acpi@...r.kernel.org,
linux-kernel@...r.kernel.org,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
linux-riscv@...ts.infradead.org
Cc: Yunhui Cui <cuiyunhui@...edance.com>
Subject: [PATCH 2/2] RISC-V: Select ACPI PPTT drivers
RSIC-V currently does not have a set of registers similar to ARM64
that describe cache-related attributes. In order to make RISC-V
cacheinfo normally supported by ACPI, through the optimization of
pptt.c, RISC-V can build cacheinfo through the ACPI PPTT table.
Signed-off-by: Yunhui Cui <cuiyunhui@...edance.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8f10a2fb5f86..cc516c12cb92 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,7 @@ config RISCV
def_bool y
select ACPI_GENERIC_GSI if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
+ select ACPI_PPTT if ACPI
select ARCH_DMA_DEFAULT_COHERENT
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
--
2.20.1
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