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Message-ID: <d55fce26-a96e-4653-a463-a277e232ed48@denx.de>
Date: Fri, 12 Apr 2024 20:35:09 +0200
From: Marek Vasut <marex@...x.de>
To: Stephen Boyd <sboyd@...nel.org>,
 Catalin Popescu <catalin.popescu@...ca-geosystems.com>,
 mturquette@...libre.com, Biju Das <biju.das.jz@...renesas.com>,
 Marek Vasut <marek.vasut+renesas@...lbox.org>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
 bsp-development.geo@...ca-geosystems.com, m.felsch@...gutronix.de
Subject: Re: [PATCH next] clk: rs9: fix wrong default value for clock
 amplitude

On 4/9/24 10:19 AM, Stephen Boyd wrote:
> Quoting Catalin Popescu (2024-03-06 10:04:35)
>> According to 9FGV0241 & 9FGV0441 datasheets

9FGV0841 too.

>, the default value
>> for the clock amplitude is 0.8V, while the driver was assuming
>> 0.7V.

Can you also document the SCC spread spectrum change in the commit message ?

>> Signed-off-by: Catalin Popescu <catalin.popescu@...ca-geosystems.com>

This also needs
Fixes: 892e0ddea1aa ("clk: rs9: Add Renesas 9-series PCIe clock 
generator driver")

Thanks ! Sorry for the delayed reply.

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