linux-kernel - Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Fri, 12 Apr 2024 14:09:32 +0800
From: Yangyu Chen <cyy@...self.name>
To: dqfext@...il.com
Cc: ajones@...tanamicro.com,
	anup@...infault.org,
	aou@...s.berkeley.edu,
	atishp@...shpatra.org,
	conor.dooley@...rochip.com,
	heiko@...ech.de,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	mark.rutland@....com,
	palmer@...belt.com,
	paul.walmsley@...ive.com,
	will@...nel.org,
	guoren@...nel.org,
	Yangyu Chen <cyy@...self.name>
Subject: Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908

On 2024/3/11 14:30, Qingfang Deng wrote:
> T-Head C908 has the same IRQ num and CSR as previous C9xx cores, but
> reports non-zero marchid and mimpid. Remove the ID checks.
> 
> Fixes: 65e9fb081877 ("drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores")
> Signed-off-by: Qingfang Deng<dqfext@...il.com>
> ---
>   arch/riscv/errata/thead/errata.c | 4 ----
>   drivers/perf/riscv_pmu_sbi.c     | 4 +---
>   2 files changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index b1c410bbc1ae..49ccad5b21bb 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -125,10 +125,6 @@ static bool errata_probe_pmu(unsigned int stage,
>   	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
>   		return false;
>   
> -	/* target-c9xx cores report arch_id and impid as 0 */
> -	if (arch_id != 0 || impid != 0)
> -		return false;
> -
>   	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
>   		return false;
>   
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 452aab49db1e..87b83184383a 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -811,9 +811,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
>   		riscv_pmu_irq_num = RV_IRQ_PMU;
>   		riscv_pmu_use_irq = true;
>   	} else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
> -		   riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
> -		   riscv_cached_marchid(0) == 0 &&
> -		   riscv_cached_mimpid(0) == 0) {
> +		   riscv_cached_mvendorid(0) == THEAD_VENDOR_ID) {
>   		riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
>   		riscv_pmu_use_irq = true;
>   	}
> -- 2.34.1

Tested-by: Yangyu Chen <cyy@...self.name>

With this patch and T-Head C908 PMU being probed by OpenSBI, I can now use
the perf record to profile RVV 1.0 software on Canaan Kendryte K230. This
will speed up many RVV 1.0 software developments now and even for better
performance.

However, as Inochi said, the newer version, C908 may support Sccofpmf. We
should ask Guo Ren to clarify this so we can have the cleanest way to
probe what to use between THEAD_PMU and Sscofpmu.

I added CC to Guo Ren. Please clarify about this.

Some off-topic things:

I need this feature recently since I am implementing a pure RVV chacha20
algorithm. I have already sent PR to openssl to speed up the crypto
performance on RVV without Zvkb support and maybe ported to kernel crypto
sometimes. To speed up TLS or other applications for many chips that may
come this year with RVV 1.0 but without Zvkb.

Link: https://github.com/openssl/openssl/pull/24069

However, the performance evaluation on K230 is not well compared to pure C
implementation. I will need this PMU driver to do some profiling.

Thanks,
Yangyu Chen