linux-kernel - Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <tencent_49E156C63C84E435E6F16509D6699339520A@qq.com>
Date: Fri, 12 Apr 2024 14:27:28 +0800
From: Yangyu Chen <cyy@...self.name>
To: conor@...nel.org
Cc: ajones@...tanamicro.com,
	anup@...infault.org,
	aou@...s.berkeley.edu,
	atishp@...shpatra.org,
	conor.dooley@...rochip.com,
	dqfext@...il.com,
	guoren@...nel.org,
	heiko@...ech.de,
	inochiama@...look.com,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	mark.rutland@....com,
	palmer@...belt.com,
	paul.walmsley@...ive.com,
	will@...nel.org
Subject: Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908

>> IMHO, it may be better to use a new DT property like "riscv,cpu-errata" or
>> "<vendor>,cpu-errata". It can achieve almost everything like using pseudo
>> isa. And the only cost I think is a small amount code to parse this.
> 
> I suppose we could do that, but accounting for vendor specifics was one
> of the goals for the property I only just added and that I am suggesting
> to use here.

I think there is a simpler way to do that. We use T-Head PMU by default
for All T-Head CPUs (from mvendor id). Then, to test there is sscofpmf in
the ISA string being probed by the kernel. If yes, then use scofpmf.
Otherwise, use T-Head PMU.

I will check if this can also be switched in any vendor CSR like Svpbmt and
T-Head MAE we discussed before.

Thanks,
Yangyu Chen