linux-kernel - RE: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

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Message-ID:
 <NTZPR01MB09568F1094DFB1F0BBFE29ED9F04A@NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn>
Date: Fri, 12 Apr 2024 08:48:19 +0000
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: Stephen Boyd <sboyd@...nel.org>, Conor Dooley <conor@...nel.org>, Emil
 Renner Berthing <emil.renner.berthing@...onical.com>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Michael Turquette
	<mturquette@...libre.com>, Rob Herring <robh@...nel.org>
CC: Emil Renner Berthing <kernel@...il.dk>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>, Hal Feng <hal.feng@...rfivetech.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL
 clock

On 10/04/2024 15:58, Stephen Boyd wrote:
> 
> Quoting Xingyu Wu (2024-04-09 20:31:47)
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > index 8f5e5abfa178..adf62e4d94e4 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct
> > jh71x0_clk_priv *priv,  }
> > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
> >
> > +/*
> > + * This clock notifier is called when the rate of PLL0 clock is to be
> > +change,
> 
> s/change,/changed./

Will fix.

> 
> > + * The cpu_root clock should save curent parent clock and swicth its
> > + parent
> 
> s/swicth/switch/

Will fix.

> 
> > + * clock to osc before PLL0 rate will be changed. And switch its
> > + parent clock
> > + * back after PLL rate finished.

Thanks,
Xingyu Wu