linux-kernel - Re: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Wed, 10 Apr 2024 00:58:12 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Conor Dooley <conor@...nel.org>, Emil Renner Berthing <emil.renner.berthing@...onical.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Michael Turquette <mturquette@...libre.com>, Rob Herring <robh@...nel.org>, Xingyu Wu <xingyu.wu@...rfivetech.com>
Cc: Emil Renner Berthing <kernel@...il.dk>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Hal Feng <hal.feng@...rfivetech.com>, Xingyu Wu <xingyu.wu@...rfivetech.com>, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v4 1/2] clk: starfive: jh7110-sys: Add notifier for PLL clock

Quoting Xingyu Wu (2024-04-09 20:31:47)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index 8f5e5abfa178..adf62e4d94e4 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
>  }
>  EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
>  
> +/*
> + * This clock notifier is called when the rate of PLL0 clock is to be change,

s/change,/changed./

> + * The cpu_root clock should save curent parent clock and swicth its parent

s/swicth/switch/

> + * clock to osc before PLL0 rate will be changed. And switch its parent clock
> + * back after PLL rate finished.