| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <bbc276d6-709b-41f0-9987-63750d78deaa@ti.com>
Date: Mon, 15 Apr 2024 13:52:12 +0530
From: Bhavya Kapoor <b-kapoor@...com>
To: Beleswar Padhi <b-padhi@...com>, <nm@...com>
CC: <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <u-kumar1@...com>
Subject: Re: [PATCH v3] arm64: dts: ti: k3-j721e-sk: Add support for multiple
CAN instances
On 12/04/24 16:50, Beleswar Padhi wrote:
> CAN instance 0 in the mcu domain is brought on the J721E-SK board
> through header J1. Thus, add its respective transceiver 1 dt node to add
> support for this CAN instance.
>
> CAN instances 0, 5 and 9 in the main domain are brought on the J721E-SK
> board through headers J5, J6 and J2 respectively. Thus, add their
> respective transceivers 2, 3 and 4 dt nodes to add support for these CAN
> instances.
>
> Signed-off-by: Beleswar Padhi <b-padhi@...com>
Reviewed-by: Bhavya Kapoor <b-kapoor@...com>
> ---
> Test logs: https://gist.github.com/3V3RYONE/2144fa883bf3a390981d25572971fcf3
>
> v3: Changelog:
> 1) Updated board name in capital letters in commit message description
> 2) Updated test logs to include communication between all applicable CAN
> instances
>
> Link to v2:
> https://lore.kernel.org/linux-arm-kernel/20240325103405.182692-1-b-padhi@ti.com/
>
> v2: Changelog:
> 1) Re-ordered status = "okay" property to the end of all applicable dt
> nodes following kernel documentation
>
> Link to v1:
> https://lore.kernel.org/linux-arm-kernel/20240315124728.490331-1-b-padhi@ti.com/
>
> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 116 +++++++++++++++++++++++++
> 1 file changed, 116 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> index 0c4575ad8d7c..7170f0220afd 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> @@ -210,6 +210,42 @@ vdd_sd_dv_alt: gpio-regulator-tps659411 {
> <3300000 0x1>;
> };
>
> + transceiver1: can-phy0 {
Hi Beleswar, all looks good to me just one little suggestion to keep
transceiver and can-phy number as same for better understanding
and to avoid some bit of confusion later.
Eg.) transceiver<x>: can-phy<x>
> + compatible = "ti,tcan1042";
> + #phy-cells = <0>;
> + max-bitrate = <5000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
> + standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>;
> + };
> +
> + transceiver2: can-phy1 {
> + compatible = "ti,tcan1042";
> + #phy-cells = <0>;
> + max-bitrate = <5000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcan0_gpio_pins_default>;
> + standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>;
> + };
> +
> + transceiver3: can-phy2 {
> + compatible = "ti,tcan1042";
> + #phy-cells = <0>;
> + max-bitrate = <5000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcan5_gpio_pins_default>;
> + standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>;
> + };
> +
> + transceiver4: can-phy3 {
> + compatible = "ti,tcan1042";
> + #phy-cells = <0>;
> + max-bitrate = <5000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcan9_gpio_pins_default>;
> + standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>;
> + };
> +
> dp_pwr_3v3: fixedregulator-dp-prw {
> compatible = "regulator-fixed";
> regulator-name = "dp-pwr";
> @@ -367,6 +403,45 @@ J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */
> >;
> };
>
> + main_mcan0_pins_default: main-mcan0-default-pins {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
> + J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
> + >;
> + };
> +
> + main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
> + >;
> + };
> +
> + main_mcan5_pins_default: main-mcan5-default-pins {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
> + J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
> + >;
> + };
> +
> + main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
> + >;
> + };
> +
> + main_mcan9_pins_default: main-mcan9-default-pins {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
> + J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
> + >;
> + };
> +
> + main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
> + >;
> + };
> +
> dp0_pins_default: dp0-default-pins {
> pinctrl-single,pins = <
> J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
> @@ -555,6 +630,19 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
> >;
> };
>
> + mcu_mcan0_pins_default: mcu-mcan0-default-pins {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
> + J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
> + >;
> + };
> +
> + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */
> + >;
> + };
> +
> /* Reset for M.2 M Key slot on PCIe1 */
> mkey_reset_pins_default: mkey-reset-pns-default-pins {
> pinctrl-single,pins = <
> @@ -1108,6 +1196,34 @@ &pcie1_rc {
> num-lanes = <2>;
> };
>
> +&mcu_mcan0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_mcan0_pins_default>;
> + phys = <&transceiver1>;
> + status = "okay";
> +};
> +
> +&main_mcan0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcan0_pins_default>;
> + phys = <&transceiver2>;
> + status = "okay";
> +};
> +
> +&main_mcan5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcan5_pins_default>;
> + phys = <&transceiver3>;
> + status = "okay";
> +};
> +
> +&main_mcan9 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mcan9_pins_default>;
> + phys = <&transceiver4>;
> + status = "okay";
> +};
> +
> &ufs_wrapper {
> status = "disabled";
> };
Powered by blists - more mailing lists