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Message-ID: <MW5PR11MB58818970CB8E9A37A6AF563889092@MW5PR11MB5881.namprd11.prod.outlook.com>
Date: Mon, 15 Apr 2024 02:22:26 +0000
From: "Zhang, Tina" <tina.zhang@...el.com>
To: Lu Baolu <baolu.lu@...ux.intel.com>, "iommu@...ts.linux.dev"
<iommu@...ts.linux.dev>
CC: "Tian, Kevin" <kevin.tian@...el.com>, "Liu, Yi L" <yi.l.liu@...el.com>,
Jacob Pan <jacob.jun.pan@...ux.intel.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
device TLB flush
> -----Original Message-----
> From: Lu Baolu <baolu.lu@...ux.intel.com>
> Sent: Monday, April 15, 2024 9:39 AM
> To: iommu@...ts.linux.dev
> Cc: Tian, Kevin <kevin.tian@...el.com>; Liu, Yi L <yi.l.liu@...el.com>; Jacob
> Pan <jacob.jun.pan@...ux.intel.com>; Joerg Roedel <joro@...tes.org>; Will
> Deacon <will@...nel.org>; Robin Murphy <robin.murphy@....com>; linux-
> kernel@...r.kernel.org; Lu Baolu <baolu.lu@...ux.intel.com>
> Subject: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
> device TLB flush
>
> The Caching Mode (CM) of the Intel IOMMU indicates if the hardware
> implementation caches not-present or erroneous translation-structure entries
> except for the first-stage translation. The caching mode is irrelevant to the
> device TLB, therefore there is no need to check it before a device TLB
> invalidation operation.
>
> Remove two caching mode checks before device TLB invalidation in the driver.
> The removal of these checks doesn't change the driver's behavior in critical
> map/unmap paths. Hence, there is no functionality or performance impact,
> especially since commit <29b32839725f> ("iommu/vt-d:
> Do not use flush-queue when caching-mode is on") has already disabled
> flush-queue for caching mode. Therefore, caching mode will never call
> intel_flush_iotlb_all().
The current logic is if the caching mode is being used and a domain isn't using first level I/O page table, then flush-queue won't be used. Otherwise, the flush-queue can be enabled.
See https://github.com/torvalds/linux/commit/257ec29074
In other words, if the caching mode is being used and a domain is using first level I/O page table, the flush-queue can be used for this domain to flush iotlb. Could the code change in this patch bring any performance impact to this case?
Regards,
-Tina
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