lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <f3502244-5f37-4f44-94a5-39939ba20eec@intel.com>
Date: Mon, 15 Apr 2024 10:43:21 +0800
From: Yi Liu <yi.l.liu@...el.com>
To: "Zhang, Tina" <tina.zhang@...el.com>, Lu Baolu <baolu.lu@...ux.intel.com>,
	"iommu@...ts.linux.dev" <iommu@...ts.linux.dev>
CC: "Tian, Kevin" <kevin.tian@...el.com>, Jacob Pan
	<jacob.jun.pan@...ux.intel.com>, Joerg Roedel <joro@...tes.org>, Will Deacon
	<will@...nel.org>, Robin Murphy <robin.murphy@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
 device TLB flush

On 2024/4/15 10:22, Zhang, Tina wrote:
> 
> 
>> -----Original Message-----
>> From: Lu Baolu <baolu.lu@...ux.intel.com>
>> Sent: Monday, April 15, 2024 9:39 AM
>> To: iommu@...ts.linux.dev
>> Cc: Tian, Kevin <kevin.tian@...el.com>; Liu, Yi L <yi.l.liu@...el.com>; Jacob
>> Pan <jacob.jun.pan@...ux.intel.com>; Joerg Roedel <joro@...tes.org>; Will
>> Deacon <will@...nel.org>; Robin Murphy <robin.murphy@....com>; linux-
>> kernel@...r.kernel.org; Lu Baolu <baolu.lu@...ux.intel.com>
>> Subject: [PATCH v3 1/1] iommu/vt-d: Remove caching mode check before
>> device TLB flush
>>
>> The Caching Mode (CM) of the Intel IOMMU indicates if the hardware
>> implementation caches not-present or erroneous translation-structure entries
>> except for the first-stage translation. The caching mode is irrelevant to the
>> device TLB, therefore there is no need to check it before a device TLB
>> invalidation operation.
>>
>> Remove two caching mode checks before device TLB invalidation in the driver.
>> The removal of these checks doesn't change the driver's behavior in critical
>> map/unmap paths. Hence, there is no functionality or performance impact,
>> especially since commit <29b32839725f> ("iommu/vt-d:
>> Do not use flush-queue when caching-mode is on") has already disabled
>> flush-queue for caching mode. Therefore, caching mode will never call
>> intel_flush_iotlb_all().
> The current logic is if the caching mode is being used and a domain isn't using first level I/O page table, then flush-queue won't be used. Otherwise, the flush-queue can be enabled.
> See https://github.com/torvalds/linux/commit/257ec29074
> 
> In other words, if the caching mode is being used and a domain is using first level I/O page table, the flush-queue can be used for this domain to flush iotlb. Could the code change in this patch bring any performance impact to this case?

This seems to have performance deduction in the nested translation case.
The iommufd nested support bas been merged in 6.8, while the Qemu side
is wip. So this performance deduction does not happen until Qemu is
done. Should this also be considered as a performance regression? TBH.
I doubt if it should be.

-- 
Regards,
Yi Liu

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ