linux-kernel - Re: [PATCH v3 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

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Message-ID: <Zh5HbV_M6wOdf9QN@bogus>
Date: Tue, 16 Apr 2024 10:39:57 +0100
From: Sudeep Holla <sudeep.holla@....com>
To: Yunhui Cui <cuiyunhui@...edance.com>
Cc: rafael@...nel.org, lenb@...nel.org, linux-acpi@...r.kernel.org,
	linux-kernel@...r.kernel.org, paul.walmsley@...ive.com,
	Sudeep Holla <sudeep.holla@....com>, palmer@...belt.com,
	aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org,
	bhelgaas@...gle.com, james.morse@....com, jhugo@...eaurora.org,
	jeremy.linton@....com, john.garry@...wei.com,
	Jonathan.Cameron@...wei.com, pierre.gondois@....com,
	tiantao6@...wei.com
Subject: Re: [PATCH v3 2/3] riscv: cacheinfo: initialize cacheinfo's level
 and type from ACPI PPTT

On Tue, Apr 16, 2024 at 11:14:37AM +0800, Yunhui Cui wrote:
> Before cacheinfo can be built correctly, we need to initialize level
> and type. Since RSIC-V currently does not have a register group that
> describes cache-related attributes like ARM64, we cannot obtain them
> directly, so now we obtain cache leaves from the ACPI PPTT table
> (acpi_get_cache_info()) and set the cache type through split_levels.
>
> Suggested-by: Jeremy Linton <jeremy.linton@....com>
> Suggested-by: Sudeep Holla <sudeep.holla@....com>

I had already given the reviewed-by for the series, anyways here we go again:

Reviewed-by: Sudeep Holla <sudeep.holla@....com>

-- 
Regards,
Sudeep