Date: Wed, 17 Apr 2024 01:53:45 -0700
From: "Ho-Ren (Jack) Chuang" <horenchuang@...edance.com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Cc: "Huang, Ying" <ying.huang@...el.com>, Gregory Price <gourry.memverge@...il.com>, 
	aneesh.kumar@...ux.ibm.com, mhocko@...e.com, tj@...nel.org, 
	john@...alactic.com, Eishan Mirakhur <emirakhur@...ron.com>, 
	Vinicius Tavares Petrucci <vtavarespetr@...ron.com>, Ravis OpenSrc <Ravis.OpenSrc@...ron.com>, 
	Alistair Popple <apopple@...dia.com>, Srinivasulu Thanneeru <sthanneeru@...ron.com>, 
	SeongJae Park <sj@...nel.org>, Dan Williams <dan.j.williams@...el.com>, 
	Vishal Verma <vishal.l.verma@...el.com>, Dave Jiang <dave.jiang@...el.com>, 
	Andrew Morton <akpm@...ux-foundation.org>, nvdimm@...ts.linux.dev, 
	linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Linux Memory Management List <linux-mm@...ck.org>, "Ho-Ren (Jack) Chuang" <horenc@...edu>, 
	"Ho-Ren (Jack) Chuang" <horenchuang@...il.com>, qemu-devel@...gnu.org, 
	Hao Xiang <hao.xiang@...edance.com>
Subject: Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory
 tiers after obtaining HMAT info

On Wed, Apr 10, 2024 at 9:51 AM Jonathan Cameron
<Jonathan.Cameron@...wei.com> wrote:
>
> On Tue, 9 Apr 2024 12:02:31 -0700
> "Ho-Ren (Jack) Chuang" <horenchuang@...edance.com> wrote:
>
> > Hi Jonathan,
> >
> > On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron
> > <Jonathan.Cameron@...wei.com> wrote:
> > >
> > > On Fri, 5 Apr 2024 15:43:47 -0700
> > > "Ho-Ren (Jack) Chuang" <horenchuang@...edance.com> wrote:
> > >
> > > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron
> > > > <Jonathan.Cameron@...wei.com> wrote:
> > > > >
> > > > > On Fri,  5 Apr 2024 00:07:06 +0000
> > > > > "Ho-Ren (Jack) Chuang" <horenchuang@...edance.com> wrote:
> > > > >
> > > > > > The current implementation treats emulated memory devices, such as
> > > > > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> > > > > > (E820_TYPE_RAM). However, these emulated devices have different
> > > > > > characteristics than traditional DRAM, making it important to
> > > > > > distinguish them. Thus, we modify the tiered memory initialization process
> > > > > > to introduce a delay specifically for CPUless NUMA nodes. This delay
> > > > > > ensures that the memory tier initialization for these nodes is deferred
> > > > > > until HMAT information is obtained during the boot process. Finally,
> > > > > > demotion tables are recalculated at the end.
> > > > > >
> > > > > > * late_initcall(memory_tier_late_init);
> > > > > > Some device drivers may have initialized memory tiers between
> > > > > > `memory_tier_init()` and `memory_tier_late_init()`, potentially bringing
> > > > > > online memory nodes and configuring memory tiers. They should be excluded
> > > > > > in the late init.
> > > > > >
> > > > > > * Handle cases where there is no HMAT when creating memory tiers
> > > > > > There is a scenario where a CPUless node does not provide HMAT information.
> > > > > > If no HMAT is specified, it falls back to using the default DRAM tier.
> > > > > >
> > > > > > * Introduce another new lock `default_dram_perf_lock` for adist calculation
> > > > > > In the current implementation, iterating through CPUlist nodes requires
> > > > > > holding the `memory_tier_lock`. However, `mt_calc_adistance()` will end up
> > > > > > trying to acquire the same lock, leading to a potential deadlock.
> > > > > > Therefore, we propose introducing a standalone `default_dram_perf_lock` to
> > > > > > protect `default_dram_perf_*`. This approach not only avoids deadlock
> > > > > > but also prevents holding a large lock simultaneously.
> > > > > >
> > > > > > * Upgrade `set_node_memory_tier` to support additional cases, including
> > > > > >   default DRAM, late CPUless, and hot-plugged initializations.
> > > > > > To cover hot-plugged memory nodes, `mt_calc_adistance()` and
> > > > > > `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()` to
> > > > > > handle cases where memtype is not initialized and where HMAT information is
> > > > > > available.
> > > > > >
> > > > > > * Introduce `default_memory_types` for those memory types that are not
> > > > > >   initialized by device drivers.
> > > > > > Because late initialized memory and default DRAM memory need to be managed,
> > > > > > a default memory type is created for storing all memory types that are
> > > > > > not initialized by device drivers and as a fallback.
> > > > > >
> > > > > > Signed-off-by: Ho-Ren (Jack) Chuang <horenchuang@...edance.com>
> > > > > > Signed-off-by: Hao Xiang <hao.xiang@...edance.com>
> > > > > > Reviewed-by: "Huang, Ying" <ying.huang@...el.com>
> > > > >
> > > > > Hi - one remaining question. Why can't we delay init for all nodes
> > > > > to either drivers or your fallback late_initcall code.
> > > > > It would be nice to reduce possible code paths.
> > > >
> > > > I try not to change too much of the existing code structure in
> > > > this patchset.
> > > >
> > > > To me, postponing/moving all memory tier registrations to
> > > > late_initcall() is another possible action item for the next patchset.
> > > >
> > > > After tier_mem(), hmat_init() is called, which requires registering
> > > > `default_dram_type` info. This is when `default_dram_type` is needed.
> > > > However, it is indeed possible to postpone the latter part,
> > > > set_node_memory_tier(), to `late_init(). So, memory_tier_init() can
> > > > indeed be split into two parts, and the latter part can be moved to
> > > > late_initcall() to be processed together.
> > > >
> > > > Doing this all memory-type drivers have to call late_initcall() to
> > > > register a memory tier. I’m not sure how many they are?
> > > >
> > > > What do you guys think?
> > >
> > > Gut feeling - if you are going to move it for some cases, move it for
> > > all of them.  Then we only have to test once ;)
> > >
> > > J
> >
> > Thank you for your reminder! I agree~ That's why I'm considering
> > changing them in the next patchset because of the amount of changes.
> > And also, this patchset already contains too many things.
>
> Makes sense.  (Interestingly we are reaching the same conclusion
> for the thread that motivated suggesting bringing them all together
> in the first place!)
>
> Get things work in a clean fashion, then consider moving everything to
> happen at the same time to simplify testing etc.
Hi Jonathan,

Thank you and I will do! Could you please take another look and see if
there are any further changes needed for this patchset? If everything
looks good to you, could you please also provide a 'Reviewed-by' for
this patch?

Per discussion, I'm going to prepare another patchset "memory tier
initialization path optimization" and will send it out once ready.

>
> Jonathan

-- 
Best regards,
Ho-Ren (Jack) Chuang
莊賀任

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