linux-kernel - Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

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Message-ID: <20240419150134.000032ff@Huawei.com>
Date: Fri, 19 Apr 2024 15:01:34 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: "Ho-Ren (Jack) Chuang" <horenchuang@...edance.com>
CC: "Huang, Ying" <ying.huang@...el.com>, Gregory Price
	<gourry.memverge@...il.com>, <aneesh.kumar@...ux.ibm.com>, <mhocko@...e.com>,
	<tj@...nel.org>, <john@...alactic.com>, Eishan Mirakhur
	<emirakhur@...ron.com>, Vinicius Tavares Petrucci <vtavarespetr@...ron.com>,
	Ravis OpenSrc <Ravis.OpenSrc@...ron.com>, Alistair Popple
	<apopple@...dia.com>, Srinivasulu Thanneeru <sthanneeru@...ron.com>, SeongJae
 Park <sj@...nel.org>, Dan Williams <dan.j.williams@...el.com>, Vishal Verma
	<vishal.l.verma@...el.com>, "Dave Jiang" <dave.jiang@...el.com>, Andrew
 Morton <akpm@...ux-foundation.org>, <nvdimm@...ts.linux.dev>,
	<linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-mm@...ck.org>, "Ho-Ren (Jack) Chuang" <horenc@...edu>, "Ho-Ren (Jack)
 Chuang" <horenchuang@...il.com>, <qemu-devel@...gnu.org>, Hao Xiang
	<hao.xiang@...edance.com>
Subject: Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after
 obtaining HMAT info

On Fri,  5 Apr 2024 00:07:06 +0000
"Ho-Ren (Jack) Chuang" <horenchuang@...edance.com> wrote:

> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics than traditional DRAM, making it important to
> distinguish them. Thus, we modify the tiered memory initialization process
> to introduce a delay specifically for CPUless NUMA nodes. This delay
> ensures that the memory tier initialization for these nodes is deferred
> until HMAT information is obtained during the boot process. Finally,
> demotion tables are recalculated at the end.
> 
> * late_initcall(memory_tier_late_init);
> Some device drivers may have initialized memory tiers between
> `memory_tier_init()` and `memory_tier_late_init()`, potentially bringing
> online memory nodes and configuring memory tiers. They should be excluded
> in the late init.
> 
> * Handle cases where there is no HMAT when creating memory tiers
> There is a scenario where a CPUless node does not provide HMAT information.
> If no HMAT is specified, it falls back to using the default DRAM tier.
> 
> * Introduce another new lock `default_dram_perf_lock` for adist calculation
> In the current implementation, iterating through CPUlist nodes requires
> holding the `memory_tier_lock`. However, `mt_calc_adistance()` will end up
> trying to acquire the same lock, leading to a potential deadlock.
> Therefore, we propose introducing a standalone `default_dram_perf_lock` to
> protect `default_dram_perf_*`. This approach not only avoids deadlock
> but also prevents holding a large lock simultaneously.
> 
> * Upgrade `set_node_memory_tier` to support additional cases, including
>   default DRAM, late CPUless, and hot-plugged initializations.
> To cover hot-plugged memory nodes, `mt_calc_adistance()` and
> `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()` to
> handle cases where memtype is not initialized and where HMAT information is
> available.
> 
> * Introduce `default_memory_types` for those memory types that are not
>   initialized by device drivers.
> Because late initialized memory and default DRAM memory need to be managed,
> a default memory type is created for storing all memory types that are
> not initialized by device drivers and as a fallback.
> 
> Signed-off-by: Ho-Ren (Jack) Chuang <horenchuang@...edance.com>
> Signed-off-by: Hao Xiang <hao.xiang@...edance.com>
> Reviewed-by: "Huang, Ying" <ying.huang@...el.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>