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Message-ID: <cbb48b6b-f31e-4f53-b114-29fe2c029387@linux.dev>
Date: Tue, 23 Apr 2024 11:18:34 -0400
From: Sean Anderson <sean.anderson@...ux.dev>
To: Rob Herring <robh@...nel.org>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Thippeswamy Havalige <thippeswamy.havalige@....com>,
Michal Simek <michal.simek@....com>, Bjorn Helgaas <bhelgaas@...gle.com>,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org
Subject: Re: [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys
On 4/23/24 08:44, Rob Herring wrote:
> On Mon, Apr 22, 2024 at 03:58:58PM -0400, Sean Anderson wrote:
>> Add phys properties so Linux can power-on/configure the GTR
>> transcievers.
>>
>> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
>> ---
>>
>> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> index 426f90a47f35..02315669b831 100644
>> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> @@ -61,6 +61,14 @@ properties:
>> interrupt-map:
>> maxItems: 4
>>
>> + phys:
>> + maxItems: 4
>> +
>> + phy-names:
>> + maxItems: 4
>> + items:
>> + - pattern: '^pcie-phy[0-3]$'
>
> The names here are pointless and redundant. Names are local to the
> device, so 'pcie' is redundant. They only refer to PHYs, so 'phy' is
> redundant too. All you are left with is the index of the entry.
>
> Now if PCIe can work on only lanes 2 and 3 or similar, then maybe
> -names becomes useful.
OK, I'll just remove them...
--Sean
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