lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240423124456.GB4105016-robh@kernel.org>
Date: Tue, 23 Apr 2024 07:44:56 -0500
From: Rob Herring <robh@...nel.org>
To: Sean Anderson <sean.anderson@...ux.dev>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof WilczyƄski <kw@...ux.com>,
	linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Thippeswamy Havalige <thippeswamy.havalige@....com>,
	Michal Simek <michal.simek@....com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	devicetree@...r.kernel.org
Subject: Re: [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys

On Mon, Apr 22, 2024 at 03:58:58PM -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
> 
> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
> ---
> 
>  Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 426f90a47f35..02315669b831 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -61,6 +61,14 @@ properties:
>    interrupt-map:
>      maxItems: 4
>  
> +  phys:
> +    maxItems: 4
> +
> +  phy-names:
> +    maxItems: 4
> +    items:
> +      - pattern: '^pcie-phy[0-3]$'

The names here are pointless and redundant. Names are local to the 
device, so 'pcie' is redundant. They only refer to PHYs, so 'phy' is 
redundant too. All you are left with is the index of the entry.

Now if PCIe can work on only lanes 2 and 3 or similar, then maybe 
-names becomes useful.

Rob

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ