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Message-ID: <7122785c-d6cf-4425-82a5-2f65e0a523d9@quicinc.com>
Date: Wed, 24 Apr 2024 13:29:21 +0530
From: Viken Dadhaniya <quic_vdadhani@...cinc.com>
To: Luca Weiss <luca.weiss@...rphone.com>,
<cros-qcom-dts-watchers@...omium.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <swboyd@...omium.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
<conor+dt@...nel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <rajpat@...eaurora.org>,
<mka@...omium.org>, <rojay@...eaurora.org>
CC: <quic_msavaliy@...cinc.com>, <quic_anupkulk@...cinc.com>
Subject: Re: [PATCH v1] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration
On 4/16/2024 5:08 PM, Luca Weiss wrote:
> On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote:
>> Remove CTS and RTS pinctrl configuration for UART5 node as
>> it's designed for debug UART for all the board variants of the
>> sc7280 chipset.
>>
>> Also change compatible string to debug UART.
>
> This change has little to do with the SoC design though and is dependent
> on the usage on a given board, right? Also the QCM6490 datasheet
> mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR.
>
> But at least consistency-wise this change makes sense, in practically
> all other SoCs one UART is marked as geni-debug-uart.
>
> But with this patch you should then also remove some overrides that are
> placed in various boards already?
>
> arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible = "qcom,geni-debug-uart";
> arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible = "qcom,geni-debug-uart";
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible = "qcom,geni-debug-uart";
> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible = "qcom,geni-debug-uart";
> arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible = "qcom,geni-debug-uart";
>
> Regards
> Luca
>
Updated in V2.
>>
>> Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node")
>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------
>> 1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 38c183b2bb26..2a6b4c4639d1 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1440,12 +1440,12 @@
>> };
>>
>> uart5: serial@...000 {
>> - compatible = "qcom,geni-uart";
>> + compatible = "qcom,geni-debug-uart";
>> reg = <0 0x00994000 0 0x4000>;
>> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
>> clock-names = "se";
>> pinctrl-names = "default";
>> - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
>> + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
>> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>> power-domains = <&rpmhpd SC7280_CX>;
>> operating-points-v2 = <&qup_opp_table>;
>> @@ -5397,16 +5397,6 @@
>> function = "qup04";
>> };
>>
>> - qup_uart5_cts: qup-uart5-cts-state {
>> - pins = "gpio20";
>> - function = "qup05";
>> - };
>> -
>> - qup_uart5_rts: qup-uart5-rts-state {
>> - pins = "gpio21";
>> - function = "qup05";
>> - };
>> -
>> qup_uart5_tx: qup-uart5-tx-state {
>> pins = "gpio22";
>> function = "qup05";
>
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