linux-kernel - RE: [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

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Message-ID:
 <NTZPR01MB0956902DF5CB459302BA263F9F17A@NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn>
Date: Thu, 25 Apr 2024 09:08:19 +0000
From: Xingyu Wu <xingyu.wu@...rfivetech.com>
To: Alexandre Ghiti <alex@...ti.fr>, Michael Turquette
	<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Conor Dooley
	<conor@...nel.org>, Emil Renner Berthing
	<emil.renner.berthing@...onical.com>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: Emil Renner Berthing <kernel@...il.dk>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>, Hal Feng <hal.feng@...rfivetech.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on

On 25/04/2024 04:32, Alexandre Ghiti wrote:
> 
> Hi Xingyu,
> 
> On 10/04/2024 05:31, Xingyu Wu wrote:
> > This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> > to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> >
> > The first patch is to add the notifier for PLL0 clock. Setting the
> > PLL0 rate need the son clock (cpu_root) to switch its parent clock to
> > OSC clock and switch it back after setting PLL0 rate. It need to use
> > the cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> > driver.
> >
> > The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
> > 1.5GHz to fix the problem about the lower rate of CPUfreq on the
> > visionfive board. The cpu_core clock rate is set to 500MHz first to
> > ensure that the cpu frequency will not suddenly become high and the
> > cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
> > The cpu voltage and frequency are then adjusted together by CPUfreq.
> >
> > Changes since v3:
> > - Added the notifier for PLL0 clock.
> > - Set cpu_core rate in DTS
> >
> > v3:
> > https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivet
> > ech.com/
> >
> > Changes since v2:
> > - Made the steps into the process into the process of setting PLL0
> > rate
> >
> > v2:
> > https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfive
> > tech.com/
> >
> > Changes since v1:
> > - Added the fixes tag in the commit.
> >
> > v1:
> > https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfive
> > tech.com/
> >
> > Xingyu Wu (2):
> >    clk: starfive: jh7110-sys: Add notifier for PLL clock
> >    riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by
> >      setting PLL0 rate to 1.5GHz
> >
> >   .../jh7110-starfive-visionfive-2.dtsi         |  6 ++++
> >   .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
> >   drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
> >   3 files changed, 38 insertions(+), 1 deletion(-)
> 
> 
> I only took a quick look so I'm not sure: does patch 2 depend on patch 1? In that
> case, I think the Fixes tag should be applied to both patches.

Hi Alex,

Yes, Patch 2 is dependent on patch 1. If patch 2 is applied alone, it does not work.
I will add the Fixes tag both patches.

> 
> And as this is a fix, will you respin a new version soon for 6.9?

Yes. I will send a new version of this patches.

Best regards,
Xingyu Wu