linux-kernel - Re: [PATCH V2 1/2] drm/bridge: samsung-dsim: Set P divider based on min/max of fin pll

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Message-ID: <e8d6826a-67d4-417f-ab40-072b8705e37d@samsung.com>
Date: Thu, 25 Apr 2024 11:18:29 +0200
From: Marek Szyprowski <m.szyprowski@...sung.com>
To: Adam Ford <aford173@...il.com>, dri-devel@...ts.freedesktop.org
Cc: marex@...x.de, aford@...conembedded.com, Frieder Schrempf
	<frieder.schrempf@...tron.de>, Inki Dae <inki.dae@...sung.com>, Jagan Teki
	<jagan@...rulasolutions.com>, Andrzej Hajda <andrzej.hajda@...el.com>, Neil
	Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
	Laurent Pinchart <Laurent.pinchart@...asonboard.com>, Jonas Karlman
	<jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>, Maarten
	Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard
	<mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, David Airlie
	<airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>, Marco Felsch
	<m.felsch@...gutronix.de>, Michael Tretter <m.tretter@...gutronix.de>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 1/2] drm/bridge: samsung-dsim: Set P divider based on
 min/max of fin pll

On 12.02.2024 00:09, Adam Ford wrote:
> The P divider should be set based on the min and max values of
> the fin pll which may vary between different platforms.
> These ranges are defined per platform, but hard-coded values
> were used instead which resulted in a smaller range available
> on the i.MX8M[MNP] than what was possible.
>
> As noted by Frieder, there are descripencies between the reference
> manuals of the Mini, Nano and Plus, so I reached out to my NXP
> rep and got the following response regarding the varing notes
> in the documentation.
>
> "Yes it is definitely wrong, the one that is part of the NOTE in
> MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is
> not correct. I will report this to Doc team, the one customer should
> be take into account is the Table 13-40 DPHY PLL Parameters and the
> Note above."
>
> With this patch, the clock rates now match the values used in NXP's
> downstream kernel.
>
> Fixes: 846307185f0f ("drm/bridge: samsung-dsim: update PLL reference clock")
> Signed-off-by: Adam Ford <aford173@...il.com>
> Reviewed-by: Frieder Schrempf <frieder.schrempf@...tron.de>
> Tested-by: Frieder Schrempf <frieder.schrempf@...tron.de>

Feel free to add:

Tested-by: Marek Szyprowski <m.szyprowski@...sung.com>

although all Exynos based boards have panels with fixed timings afair.

> ---
> V2:  Only update the commit message to reflect why these values
>       were chosen.  No code change present
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index 95fedc68b0ae..8476650c477c 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -574,8 +574,8 @@ static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
>   	u16 _m, best_m;
>   	u8 _s, best_s;
>   
> -	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
> -	p_max = fin / (6 * MHZ);
> +	p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * MHZ));
> +	p_max = fin / (driver_data->pll_fin_min * MHZ);
>   
>   	for (_p = p_min; _p <= p_max; ++_p) {
>   		for (_s = 0; _s <= 5; ++_s) {

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland