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Message-Id: <20240429152207.479221-19-james.clark@arm.com>
Date: Mon, 29 Apr 2024 16:22:03 +0100
From: James Clark <james.clark@....com>
To: linux-perf-users@...r.kernel.org,
gankulkarni@...amperecomputing.com,
scclevenger@...amperecomputing.com,
coresight@...ts.linaro.org,
suzuki.poulose@....com,
mike.leach@...aro.org
Cc: James Clark <james.clark@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Jiri Olsa <jolsa@...nel.org>,
Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
John Garry <john.g.garry@...cle.com>,
Will Deacon <will@...nel.org>,
Leo Yan <leo.yan@...ux.dev>,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com
Subject: [PATCH 17/17] coresight: Emit HW_IDs for all ETMs that are using the sink
For Perf to be able to decode when per-sink trace IDs are used, emit all
the mappings for each sink.
Perf currently errors out if it sees a newer packet version so instead
of bumping it, add a new minor version field. This can be used to
signify new versions that have backwards compatible fields. Considering
this change is only for high core count machines, it doesn't make sense
to make a breaking change for everyone.
Signed-off-by: James Clark <james.clark@....com>
---
.../hwtracing/coresight/coresight-etm-perf.c | 47 ++++++++++++++++---
include/linux/coresight-pmu.h | 17 +++++--
2 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 08f3958f9367..3bb1ae1e5264 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -444,6 +444,46 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
goto out;
}
+static void etm_output_hw_ids(struct perf_event *event,
+ struct coresight_trace_id_map *id_map,
+ int this_events_cpu)
+{
+ int cpu;
+ u8 this_events_trace_id = coresight_trace_id_read_cpu_id(this_events_cpu, id_map);
+
+ /*
+ * This isn't optimal because we likely only have a couple of IDs
+ * allocated per-sink, but we only currently track the used trace IDs as
+ * a bitmask, rather than the used CPUs in each ID map. It would also
+ * require some extra locking to iterate a used CPUs bitmask and then
+ * output the ID from a different structure. So at the moment just
+ * iterate all CPUs.
+ */
+ for_each_possible_cpu(cpu) {
+ u64 hw_id;
+ u8 trace_id = coresight_trace_id_read_cpu_id(cpu, id_map);
+
+ if (!IS_VALID_CS_TRACE_ID(trace_id))
+ continue;
+
+ hw_id = FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK,
+ CS_AUX_HW_ID_MAJOR_VERSION);
+ hw_id |= FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK,
+ CS_AUX_HW_ID_MINOR_VERSION);
+
+ /* Repeat sending the ID for this event so that it's backwards compatible */
+ hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, this_events_trace_id);
+
+ /*
+ * Output the V0.1 HW_ID info that shows which other ID mappings
+ * are valid on this sink.
+ */
+ hw_id |= FIELD_PREP(CS_AUX_HW_ID_V01_CPU_MASK, cpu);
+ hw_id |= FIELD_PREP(CS_AUX_HW_ID_V01_TRACE_ID_MASK, trace_id);
+ perf_report_aux_output_id(event, hw_id);
+ }
+}
+
static void etm_event_start(struct perf_event *event, int flags)
{
int cpu = smp_processor_id();
@@ -452,7 +492,6 @@ static void etm_event_start(struct perf_event *event, int flags)
struct perf_output_handle *handle = &ctxt->handle;
struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
struct list_head *path;
- u64 hw_id;
if (!csdev)
goto fail;
@@ -519,11 +558,7 @@ static void etm_event_start(struct perf_event *event, int flags)
*/
if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) {
cpumask_set_cpu(cpu, &event_data->aux_hwid_done);
- hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK,
- CS_AUX_HW_ID_CURR_VERSION);
- hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK,
- coresight_trace_id_read_cpu_id(cpu, &sink->perf_id_map));
- perf_report_aux_output_id(event, hw_id);
+ etm_output_hw_ids(event, &sink->perf_id_map, cpu);
}
out:
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 51ac441a37c3..4a7fac6f66b9 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -49,12 +49,21 @@
* Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload.
* Used to associate a CPU with the CoreSight Trace ID.
* [07:00] - Trace ID - uses 8 bits to make value easy to read in file.
- * [59:08] - Unused (SBZ)
- * [63:60] - Version
+ * [15:08] - V2 Trace ID - ID for the ETM/CPU referenced by V2 CPU
+ * [31:16] - V2 CPU ID - CPU that corresponds to the trace ID in V2 trace ID
+ * [55:32] - Unused (SBZ)
+ * [59:56] - Minor Version - previously existing fields are compatible with
+ * all minor versions.
+ * [63:60] - Major Version - previously existing fields mean different things
+ * in new major versions.
*/
#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
-#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60)
+#define CS_AUX_HW_ID_V01_TRACE_ID_MASK GENMASK_ULL(15, 8)
+#define CS_AUX_HW_ID_V01_CPU_MASK GENMASK_ULL(31, 16)
+#define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56)
+#define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60)
-#define CS_AUX_HW_ID_CURR_VERSION 0
+#define CS_AUX_HW_ID_MAJOR_VERSION 0
+#define CS_AUX_HW_ID_MINOR_VERSION 1
#endif
--
2.34.1
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