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Message-ID: <20240506225139.57647-12-kyarlagadda@nvidia.com>
Date: Tue, 7 May 2024 04:21:39 +0530
From: Krishna Yarlagadda <kyarlagadda@...dia.com>
To: <linux-tegra@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-doc@...r.kernel.org>, <linux-i2c@...r.kernel.org>,
<linux-mmc@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: <thierry.reding@...il.com>, <jonathanh@...dia.com>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <corbet@....net>,
<andi.shyti@...nel.org>, <wsa+renesas@...g-engineering.com>,
<ulf.hansson@...aro.org>, <adrian.hunter@...el.com>, <digetx@...il.com>,
<ldewangan@...dia.com>, <kyarlagadda@...dia.com>, <mkumard@...dia.com>
Subject: [RFC PATCH 11/11] arm64: tegra: SDHCI timing settings
Set SDHCI timing registers through config settings for
Tegra234 chip and P3701 board.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
index 832538e45797..f9a92853b04a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
@@ -442,5 +442,37 @@ standard {
};
};
+ mmc@...0000 {
+ config {
+
+ mmc-hs200 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ uhs-sdr104 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ uhs-sdr50 {
+ nvidia,num-tuning-iter = <0x4>;
+ };
+
+ };
+ };
+
+ mmc@...0000 {
+ config {
+
+ mmc-hs200 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ mmc-hs400 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ };
+ };
+
};
};
--
2.43.2
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