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Message-ID: <b367a6ba-3ff1-4173-bf71-cd7a04bf9882@amd.com>
Date: Tue, 7 May 2024 15:40:52 -0500
From: "Moger, Babu" <babu.moger@....com>
To: Reinette Chatre <reinette.chatre@...el.com>, corbet@....net,
fenghua.yu@...el.com, tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com
Cc: x86@...nel.org, hpa@...or.com, paulmck@...nel.org, rdunlap@...radead.org,
tj@...nel.org, peterz@...radead.org, yanjiewtw@...il.com,
kim.phillips@....com, lukas.bulwahn@...il.com, seanjc@...gle.com,
jmattson@...gle.com, leitao@...ian.org, jpoimboe@...nel.org,
rick.p.edgecombe@...el.com, kirill.shutemov@...ux.intel.com,
jithu.joseph@...el.com, kai.huang@...el.com, kan.liang@...ux.intel.com,
daniel.sneddon@...ux.intel.com, pbonzini@...hat.com, sandipan.das@....com,
ilpo.jarvinen@...ux.intel.com, peternewman@...gle.com,
maciej.wieczor-retman@...el.com, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, eranian@...gle.com, james.morse@....com
Subject: Re: [RFC PATCH v3 10/17] x86/resctrl: Add data structures for ABMC
assignment
Hi Reinette,
On 5/3/24 18:32, Reinette Chatre wrote:
> Hi Babu,
>
> On 3/28/2024 6:06 PM, Babu Moger wrote:
>> ABMC (Bandwidth Monitoring Event Configuration) counters can be configured
>> by writing to L3_QOS_ABMC_CFG MSR. When ABMC is enabled, the user can
>> configure a counter by writing to L3_QOS_ABMC_CFG setting the CfgEn field
>> while specifying the Bandwidth Source, Bandwidth Types, and Counter
>> Identifier. Add the MSR definition and individual field definitions.
>>
>> MSR L3_QOS_ABMC_CFG (C000_03FDh) definitions.
>>
>> ==========================================================================
>> Bits Mnemonic Description Access Type Reset Value
>> ==========================================================================
>> 63 CfgEn Configuration Enable R/W 0
>>
>> 62 CtrEn Counter Enable R/W 0
>>
>> 61:53 – Reserved MBZ 0
>>
>> 52:48 CtrID Counter Identifier R/W 0
>>
>> 47 IsCOS BwSrc field is a COS R/W 0
>> (not an RMID)
>>
>> 46:44 – Reserved MBZ 0
>>
>> 43:32 BwSrc Bandwidth Source R/W 0
>> (RMID or COS)
>>
>> 31:0 BwType Bandwidth types to R/W 0
>> track for this counter
>> ==========================================================================
>>
>> The feature details are documentd in the APM listed below [1].
>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>> Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
>> Monitoring (ABMC).
>
> This changelog is purely a summary of the hardware architecture. I have not come
> across a clear explanation on how this architecture is intended to be supported
> by resctrl. When would resctrl need/want to set particular fields? What is
> the mapping to resctrl?
Something like this in the changelog?
ABMC feature provides an option to assign(or pin) an RMID to the
hardware counter and monitor the bandwidth for a longer duration.
Hardware counters can be configured by writing to L3_QOS_ABMC_CFG MSR.
Configuration is done by setting the CfgEn field while specifying the
Bandwidth Source(RMID or CLOS), Bandwidth Types, and Counter Identifier.
Add the configuration register definition.
>
>>
>> Signed-off-by: Babu Moger <babu.moger@....com>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>>
>> ---
>> v3: No changes.
>> v2: No changes.
>> ---
>> arch/x86/include/asm/msr-index.h | 1 +
>> arch/x86/kernel/cpu/resctrl/internal.h | 23 +++++++++++++++++++++++
>> 2 files changed, 24 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index f16ee50b1a23..ab01abfab089 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -1166,6 +1166,7 @@
>> #define MSR_IA32_SMBA_BW_BASE 0xc0000280
>> #define MSR_IA32_EVT_CFG_BASE 0xc0000400
>> #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
>> +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd
>>
>> /* MSR_IA32_VMX_MISC bits */
>> #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h
>> index b559b3a4555e..41b06d46ea74 100644
>> --- a/arch/x86/kernel/cpu/resctrl/internal.h
>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
>> @@ -106,6 +106,9 @@ cpumask_any_housekeeping(const struct cpumask *mask, int exclude_cpu)
>> #define ASSIGN_TOTAL BIT(0)
>> #define ASSIGN_LOCAL BIT(1)
>>
>> +/* Maximum assignable counters per resctrl group */
>> +#define MAX_ASSIGN_CNTRS 2
>> +
>> struct rdt_fs_context {
>> struct kernfs_fs_context kfc;
>> bool enable_cdpl2;
>> @@ -210,6 +213,7 @@ enum rdtgrp_mode {
>> * @crdtgrp_list: child rdtgroup node list
>> * @rmid: rmid for this rdtgroup
>> * @mon_state: Assignment state of the group
>> + * @abmc_ctr_id: ABMC counterids assigned to this group
>> */
>> struct mongroup {
>> struct kernfs_node *mon_data_kn;
>> @@ -217,6 +221,7 @@ struct mongroup {
>> struct list_head crdtgrp_list;
>> u32 rmid;
>> u32 mon_state;
>> + u32 abmc_ctr_id[MAX_ASSIGN_CNTRS];
>> };
>>
>> /**
>> @@ -566,6 +571,24 @@ union cpuid_0x10_x_edx {
>> unsigned int full;
>> };
>>
>> +/*
>> + * L3_QOS_ABMC_CFG MSR details. ABMC counters can be configured
>> + * by writing to L3_QOS_ABMC_CFG.
>
> There are many fields in this structure ... how is resctrl expected
> to set these fields in order to configure a counter? Please expand the
> comments.
Sure.
>
>> + */
>> +union l3_qos_abmc_cfg {
>> + struct {
>> + unsigned long bw_type :32,
>> + bw_src :12,
>> + rsvrd1 : 3,
>
> Considering how "reserved" is spelled it is
> unexpected to see "rsvrd"
Will change it to "reserved1" and "reserved" (below).
>
>
>> + is_cos : 1,
>> + ctr_id : 5,
>> + rsvrd : 9,
>> + ctr_en : 1,
>> + cfg_en : 1;
>> + } split;
>> + unsigned long full;
>> +};
>> +
>> void rdt_last_cmd_clear(void);
>> void rdt_last_cmd_puts(const char *s);
>> __printf(1, 2)
>
>
> Reinette
>
--
Thanks
Babu Moger
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