linux-kernel - Re: [RFC PATCH v3 10/17] x86/resctrl: Add data structures for ABMC assignment

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <89d9996e-3414-43f9-82f6-0260a4f49285@intel.com>
Date: Tue, 7 May 2024 16:06:17 -0700
From: Reinette Chatre <reinette.chatre@...el.com>
To: <babu.moger@....com>, <corbet@....net>, <fenghua.yu@...el.com>,
	<tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
	<dave.hansen@...ux.intel.com>
CC: <x86@...nel.org>, <hpa@...or.com>, <paulmck@...nel.org>,
	<rdunlap@...radead.org>, <tj@...nel.org>, <peterz@...radead.org>,
	<yanjiewtw@...il.com>, <kim.phillips@....com>, <lukas.bulwahn@...il.com>,
	<seanjc@...gle.com>, <jmattson@...gle.com>, <leitao@...ian.org>,
	<jpoimboe@...nel.org>, <rick.p.edgecombe@...el.com>,
	<kirill.shutemov@...ux.intel.com>, <jithu.joseph@...el.com>,
	<kai.huang@...el.com>, <kan.liang@...ux.intel.com>,
	<daniel.sneddon@...ux.intel.com>, <pbonzini@...hat.com>,
	<sandipan.das@....com>, <ilpo.jarvinen@...ux.intel.com>,
	<peternewman@...gle.com>, <maciej.wieczor-retman@...el.com>,
	<linux-doc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<eranian@...gle.com>, <james.morse@....com>
Subject: Re: [RFC PATCH v3 10/17] x86/resctrl: Add data structures for ABMC
 assignment

Hi Babu,

On 5/7/2024 1:40 PM, Moger, Babu wrote:
> On 5/3/24 18:32, Reinette Chatre wrote:
>> On 3/28/2024 6:06 PM, Babu Moger wrote:
>>> ABMC (Bandwidth Monitoring Event Configuration) counters can be configured
>>> by writing to L3_QOS_ABMC_CFG MSR. When ABMC is enabled, the user can
>>> configure a counter by writing to L3_QOS_ABMC_CFG setting the CfgEn field
>>> while specifying the Bandwidth Source, Bandwidth Types, and Counter
>>> Identifier. Add the MSR definition and individual field definitions.
>>>
>>> MSR L3_QOS_ABMC_CFG (C000_03FDh) definitions.
>>>
>>> ==========================================================================
>>> Bits 	Mnemonic	Description		Access Type   Reset Value
>>> ==========================================================================
>>> 63 	CfgEn 		Configuration Enable 	R/W 		0
>>>
>>> 62 	CtrEn 		Counter Enable 		R/W 		0
>>>
>>> 61:53 	– 		Reserved 		MBZ 		0
>>>
>>> 52:48 	CtrID 		Counter Identifier	R/W		0
>>>
>>> 47 	IsCOS		BwSrc field is a COS	R/W		0
>>> 			(not an RMID)
>>>
>>> 46:44 	–		Reserved		MBZ		0
>>>
>>> 43:32	BwSrc		Bandwidth Source	R/W		0
>>> 			(RMID or COS)
>>>
>>> 31:0	BwType		Bandwidth types to	R/W		0
>>> 			track for this counter
>>> ==========================================================================
>>>
>>> The feature details are documentd in the APM listed below [1].

documentd -> documented

>>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>>> Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth
>>> Monitoring (ABMC).
>>
>> This changelog is purely a summary of the hardware architecture. I have not come
>> across a clear explanation on how this architecture is intended to be supported
>> by resctrl. When would resctrl need/want to set particular fields? What is
>> the mapping to resctrl?
> 
> Something like this in the changelog?
> 
> ABMC feature provides an option to assign(or pin) an RMID to the
> hardware counter and monitor the bandwidth for a longer duration.

Regarding "a longer duration":
https://lore.kernel.org/lkml/b5e68d85-4bf2-4e55-a9c1-b39cb7d94db6@intel.com/

> 
> Hardware counters can be configured by writing to L3_QOS_ABMC_CFG MSR.
> Configuration is done by setting the CfgEn field while specifying the
> Bandwidth Source(RMID or CLOS), Bandwidth Types, and Counter Identifier.
> 
> Add the configuration register definition.

This still looks to me like a cryptic description of the hardware architecture.
Could you please spell out to me how the above answers each of my questions?

Reinette