linux-kernel - Re: [PATCH v2 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge

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Message-ID: <1258b765-111c-4538-83e5-8e6aa3cb0936@zhaoxin.com>
Date: Thu, 9 May 2024 16:42:41 +0800
From: LeoLiu-oc <leoliu-oc@...oxin.com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: <rafael@...nel.org>, <lenb@...nel.org>, <james.morse@....com>,
	<tony.luck@...el.com>, <bp@...en8.de>, <bhelgaas@...gle.com>,
	<robert.moore@...el.com>, <linux-acpi@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
	<acpica-devel@...ts.linux.dev>, <CobeChen@...oxin.com>,
	<TonyWWang@...oxin.com>, <ErosZhang@...oxin.com>, <LeoLiu@...oxin.com>
Subject: Re: [PATCH v2 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X
 Bridge



在 2024/5/9 6:10, Bjorn Helgaas 写道:
> 
> 
> [这封邮件来自外部发件人 谨防风险]
> 
> On Mon, Dec 18, 2023 at 11:04:29AM +0800, LeoLiu-oc wrote:
>> From: LeoLiuoc <LeoLiu-oc@...oxin.com>
>>
>> Define secondary uncorrectable error mask register, secondary
>> uncorrectable error severity register and secondary error capabilities and
>> control register bits in AER capability for PCIe to PCI/PCI-X Bridge.
>> Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2,
>> 5.2.3.3 and 5.2.3.4.
> 
> Please include the spec revision.  The only one I'm aware of is r1.0.
> 
Yes，the PCIe to PCI/PCI-X Bridge Specification version is r1.0.
I will supplement the protocol version in the next edition.

Yours sincerely
Leoliu-oc

>> Signed-off-by: LeoLiuoc <LeoLiu-oc@...oxin.com>
>> ---
>>   include/uapi/linux/pci_regs.h | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>> index a39193213ff2..987c513192e8 100644
>> --- a/include/uapi/linux/pci_regs.h
>> +++ b/include/uapi/linux/pci_regs.h
>> @@ -802,6 +802,9 @@
>>   #define  PCI_ERR_ROOT_FATAL_RCV              0x00000040 /* Fatal Received */
>>   #define  PCI_ERR_ROOT_AER_IRQ                0xf8000000 /* Advanced Error Interrupt Message Number */
>>   #define PCI_ERR_ROOT_ERR_SRC 0x34    /* Error Source Identification */
>> +#define PCI_ERR_UNCOR_MASK2  0x30    /* PCIe to PCI/PCI-X Bridge */
>> +#define PCI_ERR_UNCOR_SEVER2 0x34    /* PCIe to PCI/PCI-X Bridge */
>> +#define PCI_ERR_CAP2 0x38    /* PCIe to PCI/PCI-X Bridge */
>>
>>   /* Virtual Channel */
>>   #define PCI_VC_PORT_CAP1     0x04
>> --
>> 2.34.1
>>