linux-kernel - Re: [PATCH v4] PCI: Relabel JHL6540 on Lenovo X1 Carbon 7,8

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Message-ID: <20240511054323.GE4162345@black.fi.intel.com>
Date: Sat, 11 May 2024 08:43:23 +0300
From: Mika Westerberg <mika.westerberg@...ux.intel.com>
To: Esther Shimanovich <eshimanovich@...omium.org>
Cc: Lukas Wunner <lukas@...ner.de>,
	Mario Limonciello <mario.limonciello@....com>,
	Dmitry Torokhov <dmitry.torokhov@...il.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, Rajat Jain <rajatja@...gle.com>
Subject: Re: [PATCH v4] PCI: Relabel JHL6540 on Lenovo X1 Carbon 7,8

On Sat, May 11, 2024 at 07:38:32AM +0300, Mika Westerberg wrote:
> They are not integrated Thunderbolt PCIe root ports.

For the clarity, Intel integrated Thunderbolt 3 controller first in Ice
Lake, then Thunderbolt 4 controller in Tiger Lake and forward (Alder
Lake, Raptor Lake, Meteor Lake). Anything else, including Comet Lake and
the like are using discrete controllers such as Alpine Ridge, Titan
Ridge (both Thunderbolt 3) and Maple Ridge (Thunderbolt 4), and Barlow
Ridge (Thunderbolt 5) where the controller is either soldered on the
motherboard or connected to a PCIe slot.

Sorry for not opening this up earlier.

There are some combinations where the integrated controller is disabled
and a discrete one is being used but again that should match the second
"rule".