linux-kernel - Re: [PATCH v4 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20240511-headset-self-dc2501b38a71@spud>
Date: Sat, 11 May 2024 13:52:16 +0100
From: Conor Dooley <conor@...nel.org>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Hauke Mehrtens <hauke@...ke-m.de>,
	Rafał Miłecki <zajec5@...il.com>,
	Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Florian Fainelli <florian.fainelli@...adcom.com>,
	Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
	linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/4] dt-bindings: mips: brcm: Document
 brcm,bmips-cbr-reg property

On Thu, May 09, 2024 at 10:47:46PM +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg property.
> 
> Some SoC suffer from a BUG where CBR(Core Base Register)
> address might badly/never inizialized by the Bootloader or
> reaching it from co-processor registers if the system
> boots from secondary CPU results in invalid address.
> 
> The CBR address is always the same on the SoC.
> 
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
> ---
>  .../devicetree/bindings/mips/brcm/soc.yaml    | 24 +++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> index 975945ca2888..6b961b62aff2 100644
> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> @@ -55,6 +55,16 @@ properties:
>           under the "cpus" node.
>          $ref: /schemas/types.yaml#/definitions/uint32
>  
> +      brcm,bmips-cbr-reg:
> +        description: Reference address of the CBR.
> +          Some SoC suffer from a BUG where CBR(Core Base Register)
> +          address might badly/never inizialized by the Bootloader or

"be badly or never initialized"

> +          reaching it from co-processor registers if the system

"reading"?

Otherwise,
Acked-by: Conor Dooley <conor.dooley@...rochip.com>

Cheers,
Conor.

> +          boots from secondary CPU results in invalid address.
> +          The CBR address is always the same on the SoC hence it
> +          can be provided in DT to handle these broken case.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +
>      patternProperties:
>        "^cpu@[0-9]$":
>          type: object
> @@ -64,6 +74,20 @@ properties:
>      required:
>        - mips-hpt-frequency
>  
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - brcm,bcm6358
> +          - brcm,bcm6368
> +
> +then:
> +  properties:
> +    cpus:
> +      required:
> +        - brcm,bmips-cbr-reg
> +
>  additionalProperties: true
>  
>  examples:
> -- 
> 2.43.0
> 

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)