linux-kernel - Re: [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling

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Message-ID: <0fc91b47-5169-4f30-84fc-c6c4ac2718e2@broadcom.com>
Date: Thu, 9 May 2024 14:38:56 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Christian Marangi <ansuelsmth@...il.com>,
 Hauke Mehrtens <hauke@...ke-m.de>, Rafał Miłecki
 <zajec5@...il.com>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
 Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Broadcom internal kernel review list
 <bcm-kernel-feedback-list@...adcom.com>, linux-mips@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling

On 5/9/24 13:47, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
> 
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
> 
> bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with
> legacy brcm47xx/brcm63xx and generic BMIPS target.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>

Acked-by: Florian Fainelli <florian.fainelli@...adcom.com>
-- 
Florian


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