[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <d1d8380a-4f28-4f65-8734-073bb4b0b359@broadcom.com>
Date: Thu, 9 May 2024 14:38:24 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Christian Marangi <ansuelsmth@...il.com>,
Hauke Mehrtens <hauke@...ke-m.de>, Rafał Miłecki
<zajec5@...il.com>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@...adcom.com>, linux-mips@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 3/4] mips: bmips: setup: make CBR address configurable
On 5/9/24 13:47, Christian Marangi wrote:
> Add support to provide CBR address from DT to handle broken
> SoC/Bootloader that doesn't correctly init it. This permits to use the
> RAC flush even in these condition.
>
> To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
> needs to be set in the "cpus" node. On DT init, this property presence
> will be checked and will set the bmips_cbr_addr value accordingly. Also
> bmips_rac_flush_disable will be set to false as RAC flush can be
> correctly supported.
>
> The CBR address from DT will overwrite the cached one and the
> one set in the CBR register will be ignored.
>
> Also the DT CBR address is validated on being outside DRAM window.
>
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
Acked-by: Florian Fainelli <florian.fainelli@...adcom.com>
--
Florian
Download attachment "smime.p7s" of type "application/pkcs7-signature" (4221 bytes)
Powered by blists - more mailing lists