linux-kernel - Re: [PATCH v2 1/2] Add write DP phyd register from parse dts

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <5745c652790b9a917a39d941065f3d9c53725b1c.camel@mediatek.com>
Date: Mon, 13 May 2024 14:21:41 +0000
From: LIANKUN YANG (杨连坤) <Liankun.Yang@...iatek.com>
To: "robh+dt@...nel.org" <robh+dt@...nel.org>, "krzk@...nel.org"
	<krzk@...nel.org>, Chunfeng Yun (云春峰)
	<Chunfeng.Yun@...iatek.com>, "chunkuang.hu@...nel.org"
	<chunkuang.hu@...nel.org>, Mac Shen (沈俊)
	<Mac.Shen@...iatek.com>, "tzimmermann@...e.de" <tzimmermann@...e.de>,
	"mripard@...nel.org" <mripard@...nel.org>,
	Jitao Shi (石记涛) <jitao.shi@...iatek.com>,
	"daniel@...ll.ch" <daniel@...ll.ch>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, "maarten.lankhorst@...ux.intel.com"
	<maarten.lankhorst@...ux.intel.com>, "conor+dt@...nel.org"
	<conor+dt@...nel.org>, "kishon@...nel.org" <kishon@...nel.org>,
	"airlied@...il.com" <airlied@...il.com>, "krzysztof.kozlowski+dt@...aro.org"
	<krzysztof.kozlowski+dt@...aro.org>, "vkoul@...nel.org" <vkoul@...nel.org>,
	"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@...iatek.com>,
	"angelogioacchino.delregno@...labora.com"
	<angelogioacchino.delregno@...labora.com>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-mediatek@...ts.infradead.org"
	<linux-mediatek@...ts.infradead.org>, "linux-phy@...ts.infradead.org"
	<linux-phy@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] Add write DP phyd register from parse dts

On Mon, 2024-05-13 at 08:38 +0200, Krzysztof Kozlowski wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  On 10/05/2024 13:04, Liankun Yang wrote:
> > During the testing phase, screen flickering is observed when
> > using displayport for screen casting. Relevant SSC register
> parameters
> > are set in dts to address the screen flickering issue effectively
> and
> > improve compatibility with different devices by adjusting the SSC
> gear.
> > 
> > Obtaining the DPTX node, parsing the dts to obtain PHY register
> address
> > and value can adapt to settings of different manufacturers
> projects.
> > 
> > Changeds in v2:
> > - Optimized method of writing to DP PHY register
> > https://patchwork.kernel.org/project/linux-mediatek/patch/
> > 20240403040517.3279-1-liankun.yang@...iatek.com/
> > 
> > Signed-off-by: Liankun Yang <liankun.yang@...iatek.com>
> > ---
> >  drivers/phy/mediatek/phy-mtk-dp.c | 37
> +++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/phy/mediatek/phy-mtk-dp.c
> b/drivers/phy/mediatek/phy-mtk-dp.c
> > index d7024a144335..ce78112d5938 100644
> > --- a/drivers/phy/mediatek/phy-mtk-dp.c
> > +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> > @@ -28,6 +28,10 @@
> >  #define MTK_DP_PHY_DIG_SW_RST(PHY_OFFSET + 0x38)
> >  #define DP_GLB_SW_RST_PHYDBIT(0)
> >  
> > +#define MTK_DP_PHY_DIG_GLB_DA_REG_14(PHY_OFFSET + 0xD8)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULTGENMASK(15, 0)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULTGENMASK(31, 16)
> > +
> >  #define MTK_DP_LANE0_DRIVING_PARAM_3(PHY_OFFSET + 0x138)
> >  #define MTK_DP_LANE1_DRIVING_PARAM_3(PHY_OFFSET + 0x238)
> >  #define MTK_DP_LANE2_DRIVING_PARAM_3(PHY_OFFSET + 0x338)
> > @@ -78,10 +82,39 @@
> >  #define DRIVING_PARAM_8_DEFAULT(XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT
> | \
> >   XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> >  
> > +#define SSC_SETTING"dp-ssc-setting"
> > +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR"ssc-delta-hbr"
> > +
> >  struct mtk_dp_phy {
> >  struct regmap *regs;
> > +struct device *dev;
> >  };
> >  
> > +static int mtk_dp_set_ssc_config(struct phy *phy, struct
> mtk_dp_phy *dp_phy)
> > +{
> > +int ret;
> > +u32 read_value = 0, reg_mask = 0;
> > +struct device_node *ssc_node = NULL;
> > +
> > +ssc_node = of_find_node_by_name(dp_phy->dev->of_node,
> SSC_SETTING);
> 
> No, really. Node name can change.
> 
> Best regards,
> Krzysztof
> 

Thank you for your comment.
I will change the node name.

Best regards.
Liankun yang