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Date: Mon, 13 May 2024 14:26:13 +0000
From: LIANKUN YANG (杨连坤) <Liankun.Yang@...iatek.com>
To: "robh+dt@...nel.org" <robh+dt@...nel.org>,
Mac Shen (沈俊) <Mac.Shen@...iatek.com>,
Chunfeng Yun (云春峰) <Chunfeng.Yun@...iatek.com>,
"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>, "tzimmermann@...e.de"
<tzimmermann@...e.de>, "mripard@...nel.org" <mripard@...nel.org>,
Jitao Shi (石记涛) <jitao.shi@...iatek.com>,
"daniel@...ll.ch" <daniel@...ll.ch>, "p.zabel@...gutronix.de"
<p.zabel@...gutronix.de>, "maarten.lankhorst@...ux.intel.com"
<maarten.lankhorst@...ux.intel.com>, "conor+dt@...nel.org"
<conor+dt@...nel.org>, "kishon@...nel.org" <kishon@...nel.org>,
"airlied@...il.com" <airlied@...il.com>, "krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>, "vkoul@...nel.org" <vkoul@...nel.org>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
"angelogioacchino.delregno@...labora.com"
<angelogioacchino.delregno@...labora.com>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>, "linux-phy@...ts.infradead.org"
<linux-phy@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] Add write DP phyd register from parse dts
On Mon, 2024-05-13 at 15:11 +0200, AngeloGioacchino Del Regno wrote:
> Il 10/05/24 13:04, Liankun Yang ha scritto:
> > During the testing phase, screen flickering is observed when
> > using displayport for screen casting. Relevant SSC register
> > parameters
> > are set in dts to address the screen flickering issue effectively
> > and
> > improve compatibility with different devices by adjusting the SSC
> > gear.
> >
> > Obtaining the DPTX node, parsing the dts to obtain PHY register
> > address
> > and value can adapt to settings of different manufacturers
> > projects.
> >
> > Changeds in v2:
> > - Optimized method of writing to DP PHY register
> >
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/__;!!CTRNKA9wMg0ARbw!jYnU_tl6YGTUcFparAOcusS3u-H9G26yso2BwugBLoeMOanZudxtqRpEYV1Zy6phDjCQH2amG0KdSaR0s7EZGycYxzaBhBvtuw$
> >
> > 20240403040517.3279-1-liankun.yang@...iatek.com/
> >
> > Signed-off-by: Liankun Yang <liankun.yang@...iatek.com>
>
> There's no devicetree support in this driver - infact, it's being
> probed by
> mtk-dp as a platform device.
>
> You keep sending untested stuff. Fourth time in a row.
>
> Please, TEST YOUR COMMITS upstream before sending!
>
> Regards,
> Angelo
>
Thank you for your comment.
It's being probed by mtk-dp as a platform device.
But through dts analysis is a better solution.
I TEST COMMITS upstream before sending in the next version.
Best Regards,
Liankun Yang
> > ---
> > drivers/phy/mediatek/phy-mtk-dp.c | 37
> > +++++++++++++++++++++++++++++++
> > 1 file changed, 37 insertions(+)
> >
> > diff --git a/drivers/phy/mediatek/phy-mtk-dp.c
> > b/drivers/phy/mediatek/phy-mtk-dp.c
> > index d7024a144335..ce78112d5938 100644
> > --- a/drivers/phy/mediatek/phy-mtk-dp.c
> > +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> > @@ -28,6 +28,10 @@
> > #define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38)
> > #define DP_GLB_SW_RST_PHYD BIT(0)
> >
> > +#define MTK_DP_PHY_DIG_GLB_DA_REG_14 (PHY_OFFSET + 0xD8)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT GENMASK(15, 0)
> > +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT GENMASK(31, 16)
> > +
> > #define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET +
> > 0x138)
> > #define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET +
> > 0x238)
> > #define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET +
> > 0x338)
> > @@ -78,10 +82,39 @@
> > #define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEF
> > AULT | \
> > XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
> >
> > +#define SSC_SETTING "dp-ssc-setting"
> > +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR "ssc-delta-hbr"
> > +
> > struct mtk_dp_phy {
> > struct regmap *regs;
> > + struct device *dev;
> > };
> >
> > +static int mtk_dp_set_ssc_config(struct phy *phy, struct
> > mtk_dp_phy *dp_phy)
> > +{
> > + int ret;
> > + u32 read_value = 0, reg_mask = 0;
> > + struct device_node *ssc_node = NULL;
> > +
> > + ssc_node = of_find_node_by_name(dp_phy->dev->of_node,
> > SSC_SETTING);
> > + if (!ssc_node) {
> > + dev_err(&phy->dev, "SSC node is NULL\n");
> > + return -ENODEV;
> > + }
> > +
> > + ret = of_property_read_u32(ssc_node,
> > RG_XTP_GLB_TXPLL_SSC_DELTA_HBR, &read_value);
> > + if (ret < 0 || !read_value) {
> > + dev_err(&phy->dev, "Read SSC vlaue fail!\n");
> > + return -EINVAL;
> > + }
> > + read_value |= read_value << 16;
> > + reg_mask |= XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT;
> > +
> > + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_GLB_DA_REG_14,
> > reg_mask, read_value);
> > +
> > + return 0;
> > +}
> > +
> > static int mtk_dp_phy_init(struct phy *phy)
> > {
> > struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
> > @@ -137,6 +170,8 @@ static int mtk_dp_phy_configure(struct phy
> > *phy, union phy_configure_opts *opts)
> > regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1,
> > TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN :
> > 0);
> >
> > + mtk_dp_set_ssc_config(phy, dp_phy);
> > +
> > return 0;
> > }
> >
> > @@ -186,6 +221,8 @@ static int mtk_dp_phy_probe(struct
> > platform_device *pdev)
> > if (!dev->of_node)
> > phy_create_lookup(phy, "dp", dev_name(dev));
> >
> > + dp_phy->dev = dev;
> > +
> > return 0;
> > }
> >
>
>
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