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Message-ID: <CAHp75VduQV9AULWNrnCZpMjSnUSpodsQQPwOH=Vs6E5JsrGmwA@mail.gmail.com>
Date: Tue, 14 May 2024 11:57:34 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: Patrick Rudolph <patrick.rudolph@...ements.com>, Mark Brown <broonie@...nel.org>, 
	naresh.solanki@...ements.com, linux-gpio@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] pinctrl: cy8c95x0: Cache muxed registers

On Tue, May 14, 2024 at 11:55 AM Andy Shevchenko
<andy.shevchenko@...il.com> wrote:
> On Tue, May 14, 2024 at 11:51 AM Linus Walleij <linus.walleij@...aro.org> wrote:
> > On Tue, May 14, 2024 at 10:39 AM Patrick Rudolph
> > <patrick.rudolph@...ements.com> wrote:
> >
> > > Do you have an example where muxed registers are used in a regmap?
> > > Is there some documentation available explaining the existing
> > > mechanism? I'm not aware of anything.
> >
> > The regmap is sadly undocumented I have had it on my list for a long
> > time to document this gem, but I never find the time.
> >
> > You have to mark registers that cannot be cached as volatile, then
> > enable caching in the regmap with e.g. .cache_type = REGCACHE_FLAT
> > in the regmap config, then it pretty much caches itself.
> > <linux/regmap.h> has some cache maintenance functions if you
> > run into corner cases.
> >
> > (Mark will correct me if I say something wrong...)
>
> It's about introducing pages of virtual registers (from regmap p.o.v.)
> to access the banks of selectable registers. The cache most likely
> will be the same, i.e. MAPPLE_TREE.

More specifically I'm talking about this data structure, and we have
several drivers in kernel that may be used as an example.

https://elixir.bootlin.com/linux/latest/source/include/linux/regmap.h#L485


-- 
With Best Regards,
Andy Shevchenko

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