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Message-ID: <20240520101149.3243151-1-s-vadapalli@ti.com>
Date: Mon, 20 May 2024 15:41:46 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <danishanwar@...com>,
<srk@...com>, <s-vadapalli@...com>
Subject: [PATCH v2 0/3] Add PCIe DT support for TI's J784S4 SoC
Hello,
TI's J784S4 SoC has two Gen3 x4 Lane PCIe Controllers. This series adds
the necessary device-tree support to enable both PCIe instances in Root
Complex mode of operation by default. The device-tree overlay to enable
both instances in Endpoint mode of operation is also present in this
series.
v1:
https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@ti.com
Changes since v1:
- Rebased series on linux-next tagged next-2024020.
- All dependencies mentioned in v1 series have been met. This series has
no further dependencies for functionality.
- Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller
node (scm_conf). This enables reusing the existing
"ti,syscon-pcie-ctrl" property without having to map the entire System
Controller region for configuring the PCIe specific registers within
"scm_conf". This change is also done in the "overlay" file in patch
3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl
nodes to the "ti,syscon-pcie-ctrl" property in the overlay.
Test Logs:
1. PCIe0 and PCIe1 in Root Complex Modes of operation with an NVMe SSD
connected to the PCIe0 instance and the Read Performance measured with
hdparm command:
https://gist.github.com/Siddharth-Vadapalli-at-TI/96c4ca37dd855120516ccdc298548dc6
2. PCIe0 Endpoint Mode functionality verified with the overlay. Logs of
the RC enumerating PCIe0 as an Endpoint:
https://gist.github.com/Siddharth-Vadapalli-at-TI/01b6fb0c9494ab76607b574a728b84da
3. PCIe1 Endpoint Mode functionality verified with the overlay. Logs of
the RC enumerating PCIe1 as an Endpoint:
https://gist.github.com/Siddharth-Vadapalli-at-TI/e844ac92d56131cbb2c134fab621b1e6
Regards,
Siddharth.
Siddharth Vadapalli (3):
arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode
arch/arm64/boot/dts/ti/Makefile | 7 +-
.../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 94 +++++++++++++++++++
4 files changed, 225 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
--
2.40.1
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