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Message-Id: <20240521-loongarch-booting-fixes-v1-4-659c201c0370@flygoat.com> Date: Tue, 21 May 2024 21:12:15 +0100 From: Jiaxun Yang <jiaxun.yang@...goat.com> To: Huacai Chen <chenhuacai@...nel.org>, Binbin Zhou <zhoubinbin@...ngson.cn> Cc: loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org, Jiaxun Yang <jiaxun.yang@...goat.com>, stable@...r.kernel.org Subject: [PATCH 4/4] LoongArch: Clear higher address bits in JUMP_VIRT_ADDR In JUMP_VIRT_ADDR we are performing an or calculation on address value directly from pcaddi. This will only work if we are currently running from direct translation addresses or firmware's DMW is configured exactly same as kernel. Still, we should not rely on such assumption. Fix by clearing higher bits in address comes from pcaddi, so we can get real physcal address before applying or operator. Cc: stable@...r.kernel.org Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com> --- arch/loongarch/include/asm/stackframe.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/stackframe.h b/arch/loongarch/include/asm/stackframe.h index 45b507a7b06f..a325d20a4503 100644 --- a/arch/loongarch/include/asm/stackframe.h +++ b/arch/loongarch/include/asm/stackframe.h @@ -42,8 +42,10 @@ .macro JUMP_VIRT_ADDR temp1 temp2 li.d \temp1, CACHE_BASE pcaddi \temp2, 0 + PTR_SLL \temp2, \temp2, (BITS_PER_LONG - DMW_PABITS) + PTR_SRL \temp2, \temp2, (BITS_PER_LONG - DMW_PABITS) or \temp1, \temp1, \temp2 - jirl zero, \temp1, 0xc + jirl zero, \temp1, 0x14 .endm .macro BACKUP_T0T1 -- 2.43.0
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