linux-kernel - RE: [PATCH net-next v19 01/13] rtase: Add pci table supported in this module

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Message-ID: <f9133a36bbae41138c3080f8f6282bfd@realtek.com>
Date: Wed, 22 May 2024 04:43:11 +0000
From: Larry Chiu <larry.chiu@...ltek.com>
To: Andrew Lunn <andrew@...n.ch>
CC: Justin Lai <justinlai0215@...ltek.com>,
        "kuba@...nel.org"
	<kuba@...nel.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "pabeni@...hat.com"
	<pabeni@...hat.com>,
        "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>,
        "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>,
        "jiri@...nulli.us" <jiri@...nulli.us>,
        "horms@...nel.org" <horms@...nel.org>,
        Ping-Ke Shih <pkshih@...ltek.com>
Subject: RE: [PATCH net-next v19 01/13] rtase: Add pci table supported in this module


> On Tue, May 21, 2024 at 06:20:04AM +0000, Larry Chiu wrote:
> >
> > >> + *  Below is a simplified block diagram of the chip and its relevant
> interfaces.
> > >> + *
> > >> + *               *************************
> > >> + *               *                       *
> > >> + *               *  CPU network device   *
> > >> + *               *                       *
> > >> + *               *   +-------------+     *
> > >> + *               *   |  PCIE Host  |     *
> > >> + *               ***********++************
> > >> + *                          ||
> > >> + *                         PCIE
> > >> + *                          ||
> > >> + *      ********************++**********************
> > >> + *      *            | PCIE Endpoint |             *
> > >> + *      *            +---------------+             *
> > >> + *      *                | GMAC |                  *
> > >> + *      *                +--++--+  Realtek         *
> > >> + *      *                   ||     RTL90xx Series  *
> > >> + *      *                   ||                     *
> > >> + *      *     +-------------++----------------+    *
> > >> + *      *     |           | MAC |             |    *
> > >> + *      *     |           +-----+             |    *
> > >> + *      *     |                               |    *
> > >> + *      *     |     Ethernet Switch Core      |    *
> > >> + *      *     |                               |    *
> > >> + *      *     |   +-----+           +-----+   |    *
> > >> + *      *     |   | MAC |...........| MAC |   |    *
> > >> + *      *     +---+-----+-----------+-----+---+    *
> > >> + *      *         | PHY |...........| PHY |        *
> > >> + *      *         +--++-+           +--++-+        *
> > >> + *      *************||****************||***********
> > >> + *
> > >> + *  The block of the Realtek RTL90xx series is our entire chip
> > >> + architecture,
> > >> + *  the GMAC is connected to the switch core, and there is no PHY in
> between.
> > >
> > >Given this architecture, this driver cannot be used unless there is a switch
> > >driver as well. This driver is nearly ready to be merged. So what are your
> > >plans for the switch driver? Do you have a first version you can post? That
> > >will reassure us you do plan to release a switch driver, and not use a SDK in
> > >userspace.
> > >
> > >        Andrew
> >
> > Hi Andrew,
> > This GMAC is configured after the switch is boot-up and does not require a
> > switch driver to work.
> 
> But if you cannot configure the switch, it is pointless passing the switch
> packets. The Linux architecture is that Linux needs to be able to control the
> switch somehow. There needs to be a driver with the switchdev API on its
> upper side which connects it to the Linux network stack. Ideally the lower
> side of this driver can directly write switch registers. Alternatively it can make
> some sort of RPC to firmware which configures the switch.
> 
> Before committing this MAC driver, we will want to be convinced there is a
> switchdev driver for the switch.
> 
>         Andrew


I know what you mean.
But actually this GMAC works like a NIC connected to an Ethernet Switch not a 
management port, its packets communicating with other ports.

The PCIe Endpoint is a multi-function device, the other function is used to 
control the switch register, we are still working on where to put this driver in 
Linux. We thought it should be separated into different device drivers, or you 
think we should register two pcie functions in this driver.

Larry