[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CABgGipW4ZTFLh1dkiRuWD0WP4RRkfhyFCc+RsUjCD2EkA5GhSQ@mail.gmail.com>
Date: Fri, 24 May 2024 17:46:16 +0800
From: Andy Chiu <andy.chiu@...ive.com>
To: Deepak Gupta <debug@...osinc.com>
Cc: paul.walmsley@...ive.com, rick.p.edgecombe@...el.com, broonie@...nel.org,
Szabolcs.Nagy@....com, kito.cheng@...ive.com, keescook@...omium.org,
ajones@...tanamicro.com, conor.dooley@...rochip.com, cleger@...osinc.com,
atishp@...shpatra.org, alex@...ti.fr, bjorn@...osinc.com,
alexghiti@...osinc.com, samuel.holland@...ive.com, conor@...nel.org,
linux-doc@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-mm@...ck.org,
linux-arch@...r.kernel.org, linux-kselftest@...r.kernel.org, corbet@....net,
palmer@...belt.com, aou@...s.berkeley.edu, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, oleg@...hat.com, akpm@...ux-foundation.org,
arnd@...db.de, ebiederm@...ssion.com, Liam.Howlett@...cle.com, vbabka@...e.cz,
lstoakes@...il.com, shuah@...nel.org, brauner@...nel.org,
jerry.shih@...ive.com, hankuan.chen@...ive.com, greentime.hu@...ive.com,
evan@...osinc.com, xiao.w.wang@...el.com, charlie@...osinc.com,
apatel@...tanamicro.com, mchitale@...tanamicro.com, dbarboza@...tanamicro.com,
sameo@...osinc.com, shikemeng@...weicloud.com, willy@...radead.org,
vincent.chen@...ive.com, guoren@...nel.org, samitolvanen@...gle.com,
songshuaishuai@...ylab.org, gerg@...nel.org, heiko@...ech.de, bhe@...hat.com,
jeeheng.sia@...rfivetech.com, cyy@...self.name, maskray@...gle.com,
ancientmodern4@...il.com, mathis.salmen@...sal.de, cuiyunhui@...edance.com,
bgray@...ux.ibm.com, mpe@...erman.id.au, baruch@...s.co.il, alx@...nel.org,
david@...hat.com, catalin.marinas@....com, revest@...omium.org,
josh@...htriplett.org, shr@...kernel.io, deller@....de, omosnace@...hat.com,
ojeda@...nel.org, jhubbard@...dia.com
Subject: Re: [PATCH v3 22/29] riscv sigcontext: adding cfi state field in sigcontext
Hi Deepak,
On Thu, Apr 4, 2024 at 7:42 AM Deepak Gupta <debug@...osinc.com> wrote:
>
> Shadow stack needs to be saved and restored on signal delivery and signal
> return.
>
> sigcontext embedded in ucontext is extendible. Adding cfi state in there
> which can be used to save cfi state before signal delivery and restore
> cfi state on sigreturn
>
> Signed-off-by: Deepak Gupta <debug@...osinc.com>
> ---
> arch/riscv/include/uapi/asm/sigcontext.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h
> index cd4f175dc837..5ccdd94a0855 100644
> --- a/arch/riscv/include/uapi/asm/sigcontext.h
> +++ b/arch/riscv/include/uapi/asm/sigcontext.h
> @@ -21,6 +21,10 @@ struct __sc_riscv_v_state {
> struct __riscv_v_ext_state v_state;
> } __attribute__((aligned(16)));
>
> +struct __sc_riscv_cfi_state {
> + unsigned long ss_ptr; /* shadow stack pointer */
> + unsigned long rsvd; /* keeping another word reserved in case we need it */
> +};
> /*
> * Signal context structure
> *
> @@ -29,6 +33,7 @@ struct __sc_riscv_v_state {
> */
> struct sigcontext {
> struct user_regs_struct sc_regs;
> + struct __sc_riscv_cfi_state sc_cfi_state;
I am concerned about this change as this could potentially break uabi.
Let's say there is a pre-CFI program running on this kernel. It
receives a signal so the kernel lays out the sig-stack as presented in
this structure. If the program accesses sc_fpregs, it would now get
sc_cfi_state. As the offset has changed, and the pre-CFI program has
not been re-compiled.
> union {
> union __riscv_fp_state sc_fpregs;
> struct __riscv_extra_ext_header sc_extdesc;
> --
> 2.43.2
>
There may be two ways to deal with this. One is to use a different
signal ABI for CFI-enabled programs. This may complicate the user
space because new programs will have to determine whether it should
use the CFI-ABI at run time. Another way is to follow what Vector does
for signal stack. It adds a way to introduce new extensions on signal
stack without impacting ABI.
Please let me know if I misunderstand anything, thanks.
Cheers,
Andy
Powered by blists - more mailing lists