| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID:
<AM9PR04MB860424A71753DBB56D2CEF5895F52@AM9PR04MB8604.eurprd04.prod.outlook.com>
Date: Fri, 24 May 2024 12:08:14 +0000
From: Pankaj Gupta <pankaj.gupta@....com>
To: Sascha Hauer <s.hauer@...gutronix.de>
CC: Jonathan Corbet <corbet@....net>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley
<conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, Pengutronix Kernel
Team <kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [EXT] Re: [PATCH v2 4/5] firmware: imx: add driver for NXP
EdgeLock Enclave
> -----Original Message-----
> From: Sascha Hauer <s.hauer@...gutronix.de>
> Sent: Friday, May 24, 2024 4:04 PM
> To: Pankaj Gupta <pankaj.gupta@....com>
> Cc: Jonathan Corbet <corbet@....net>; Rob Herring <robh+dt@...nel.org>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>; Conor Dooley
> <conor+dt@...nel.org>; Shawn Guo <shawnguo@...nel.org>; Pengutronix
> Kernel Team <kernel@...gutronix.de>; Fabio Estevam
> <festevam@...il.com>; Rob Herring <robh@...nel.org>; Krzysztof Kozlowski
> <krzk+dt@...nel.org>; linux-doc@...r.kernel.org; linux-
> kernel@...r.kernel.org; devicetree@...r.kernel.org; imx@...ts.linux.dev;
> linux-arm-kernel@...ts.infradead.org
> Subject: [EXT] Re: [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock
> Enclave
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> On Thu, May 23, 2024 at 04:19:35PM +0530, Pankaj Gupta wrote:
> > NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE), are
> > embedded in the SoC to support the features like HSM, SHE & V2X, using
> > message based communication interface.
> >
> > The secure enclave FW communicates on a dedicated messaging unit(MU)
> > based interface(s) with application core, where kernel is running.
> > It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
> >
> > This patch adds the driver for communication interface to
> > secure-enclave, for exchanging messages with NXP secure enclave HW
> > IP(s) like EdgeLock Enclave (ELE) from Kernel-space, used by kernel
> > management layers like
> > - DM-Crypt.
> >
> > Signed-off-by: Pankaj Gupta <pankaj.gupta@....com>
> > ---
> > drivers/firmware/imx/Kconfig | 12 +
> > drivers/firmware/imx/Makefile | 2 +
> > drivers/firmware/imx/ele_base_msg.c | 286 +++++++++++++++++++
> > drivers/firmware/imx/ele_base_msg.h | 92 +++++++
> > drivers/firmware/imx/ele_common.c | 239 ++++++++++++++++
> > drivers/firmware/imx/ele_common.h | 43 +++
> > drivers/firmware/imx/se_ctrl.c | 531
> ++++++++++++++++++++++++++++++++++++
> > drivers/firmware/imx/se_ctrl.h | 99 +++++++
> > include/linux/firmware/imx/se_api.h | 14 +
> > 9 files changed, 1318 insertions(+)
> >
>
> > +static int se_probe_if_cleanup(struct platform_device *pdev) {
> > + struct device *dev = &pdev->dev;
> > + struct se_if_priv *priv;
> > + int ret = 0;
> > +
> > + priv = dev_get_drvdata(dev);
> > + if (!priv) {
> > + ret = 0;
> > + dev_dbg(dev, "SE-MU Priv data is NULL;");
> > + return ret;
> > + }
> > +
> > + if (priv->tx_chan)
> > + mbox_free_channel(priv->tx_chan);
> > + if (priv->rx_chan)
> > + mbox_free_channel(priv->rx_chan);
> > +
> > + /* free the buffer in se remove, previously allocated
> > + * in se probe to store encrypted IMEM
> > + */
> > + if (priv->imem.buf) {
> > + dmam_free_coherent(dev,
> > + ELE_IMEM_SIZE,
> > + priv->imem.buf,
> > + priv->imem.phyaddr);
> > + priv->imem.buf = NULL;
> > + }
> > +
> > + if (priv->flags & RESERVED_DMA_POOL) {
> > + of_reserved_mem_device_release(dev);
>
> You can call this unconditionally, no need to keep track if you called
> of_reserved_mem_device_init() successfully.
But it will not be called for each SoC.
The memory is not reserved for i.MX95 platforms.
This is required.
>
> > +
> > +static int se_if_probe(struct platform_device *pdev) {
> > + struct imx_se_node_info_list *info_list;
> > + struct device *dev = &pdev->dev;
> > + struct imx_se_node_info *info;
> > + struct se_if_priv *priv;
> > + u32 idx;
> > + int ret;
> > +
> > + if (of_property_read_u32(dev->of_node, "reg", &idx)) {
> > + ret = -EINVAL;
> > + goto exit;
> > + }
> > +
> > + info_list = (struct imx_se_node_info_list *)
> > + device_get_match_data(dev);
> > + info = get_imx_se_node_info(info_list, idx);
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv) {
> > + ret = -ENOMEM;
> > + goto exit;
> > + }
> > +
> > + dev_set_drvdata(dev, priv);
> > +
> > + /* Mailbox client configuration */
> > + priv->se_mb_cl.dev = dev;
> > + priv->se_mb_cl.tx_block = false;
> > + priv->se_mb_cl.knows_txdone = true;
> > + priv->se_mb_cl.rx_callback = se_if_rx_callback;
> > +
> > + ret = se_if_request_channel(dev, &priv->tx_chan,
> > + &priv->se_mb_cl, info->mbox_tx_name);
> > + if (ret)
> > + goto exit;
> > +
> > + ret = se_if_request_channel(dev, &priv->rx_chan,
> > + &priv->se_mb_cl, info->mbox_rx_name);
> > + if (ret)
> > + goto exit;
> > +
> > + priv->dev = dev;
> > + priv->info = info;
> > +
> > + /* Initialize the mutex. */
> > + mutex_init(&priv->se_if_lock);
> > + mutex_init(&priv->se_if_cmd_lock);
> > +
> > + priv->cmd_receiver_dev = NULL;
> > + priv->waiting_rsp_dev = NULL;
> > + priv->max_dev_ctx = info->max_dev_ctx;
> > + priv->cmd_tag = info->cmd_tag;
> > + priv->rsp_tag = info->rsp_tag;
> > + priv->mem_pool_name = info->pool_name;
> > + priv->success_tag = info->success_tag;
> > + priv->base_api_ver = info->base_api_ver;
> > + priv->fw_api_ver = info->fw_api_ver;
> > +
> > + init_completion(&priv->done);
> > + spin_lock_init(&priv->lock);
> > +
> > + if (info->reserved_dma_ranges) {
> > + ret = of_reserved_mem_device_init(dev);
> > + if (ret) {
> > + dev_err(dev,
> > + "failed to init reserved memory region %d\n",
> > + ret);
> > + priv->flags &= (~RESERVED_DMA_POOL);
> > + goto exit;
> > + }
> > + priv->flags |= RESERVED_DMA_POOL;
> > + }
>
> Can't this be optional? Why do you need to reserve memory in the device tree
> for it?
>
No, on i.MX8ULP, there is specific reserved memory region that is accessible by secure-enclave.
> Sascha
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 |
> http://www.pe/
> ngutronix.de%2F&data=05%7C02%7Cpankaj.gupta%40nxp.com%7C76d3450
> b718d4ae732e108dc7bdd1878%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
> C0%7C0%7C638521436738802427%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%
> 7C%7C%7C&sdata=lacl2GCEAG8iTW9DpwwsrcaS1LbYqg3fw6BJwSUStKI%3D
> &reserved=0 |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Powered by blists - more mailing lists