| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id:
<171710343068.6624.13466290859953012929.git-patchwork-notify@kernel.org>
Date: Thu, 30 May 2024 21:10:30 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Alexandre Ghiti <alexghiti@...osinc.com>
Cc: linux-riscv@...ts.infradead.org, paul.walmsley@...ive.com,
palmer@...belt.com, aou@...s.berkeley.edu, leobras@...hat.com,
linux-kernel@...r.kernel.org, parri.andrea@...il.com
Subject: Re: [PATCH -fixes v2] riscv: Fix fully ordered LR/SC xchg[8|16]()
implementations
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@...osinc.com>:
On Thu, 30 May 2024 16:55:46 +0200 you wrote:
> The fully ordered versions of xchg[8|16]() using LR/SC lack the
> necessary memory barriers to guarantee the order.
>
> Fix this by matching what is already implemented in the fully ordered
> versions of cmpxchg() using LR/SC.
>
> Suggested-by: Andrea Parri <parri.andrea@...il.com>
> Reported-by: Andrea Parri <parri.andrea@...il.com>
> Closes: https://lore.kernel.org/linux-riscv/ZlYbupL5XgzgA0MX@andrea/T/#u
> Fixes: a8ed2b7a2c13 ("riscv/cmpxchg: Implement xchg for variables of size 1 and 2")
> Signed-off-by: Alexandre Ghiti <alexghiti@...osinc.com>
>
> [...]
Here is the summary with links:
- [-fixes,v2] riscv: Fix fully ordered LR/SC xchg[8|16]() implementations
https://git.kernel.org/riscv/c/1d84afaf0252
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
Powered by blists - more mailing lists