linux-kernel - Re: [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

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Message-ID: <CA+V-a8tDYjEmuZVoBk+gv-XCneEchiS91J15p8p96aKFRbo8DQ@mail.gmail.com>
Date: Tue, 4 Jun 2024 18:29:24 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v4 2/2] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

Hi Thomas,

Thank you for the review.

On Mon, Jun 3, 2024 at 1:40 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
> On Tue, Apr 30 2024 at 15:14, Prabhakar wrote:
> > +
> > +static void rzfive_irqc_irq_disable(struct irq_data *d)
> > +{
> > +     rzfive_tint_irq_endisable(d, false);
> > +     irq_chip_disable_parent(d);
> > +}
> > +
> > +static void rzfive_irqc_irq_enable(struct irq_data *d)
> > +{
> > +     rzfive_tint_irq_endisable(d, true);
> > +     irq_chip_enable_parent(d);
> > +}
>
> This looks wrong. Enable/disable should be symmetric vs. ordering, no?
>
Agreed, I will reverse the order in the disable callback and send a new version.

Cheers,
Prabhakar