linux-kernel - Re: [PATCH v4 7/7] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <90781872-1933-4026-beb0-627932411187@ti.com>
Date: Tue, 4 Jun 2024 10:52:57 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: Andrew Davis <afd@...com>
CC: Siddharth Vadapalli <s-vadapalli@...com>, <nm@...com>, <vigneshr@...com>,
        <kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <rogerq@...nel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <u-kumar1@...com>,
        <danishanwar@...com>, <srk@...com>
Subject: Re: [PATCH v4 7/7] arm64: dts: ti: k3-j722s: Enable PCIe and USB
 support on J722S-EVM

On Mon, Jun 03, 2024 at 09:21:11AM -0500, Andrew Davis wrote:
> On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> > Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
> > of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
> > interface with the Type-C port via the USB hub, by configuring the pin P05
> > of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed

[...]

> > +
> > +&serdes0 {
> > +	status = "okay";
> > +	serdes0_usb_link: phy@0 {
> > +		reg = <0>;
> > +		cdns,num-lanes = <1>;
> > +		#phy-cells = <0>;
> > +		cdns,phy-type = <PHY_TYPE_USB3>;
> > +		resets = <&serdes_wiz0 1>;
> > +	};
> > +};
> > +
> > +&serdes1 {
> > +	serdes1_pcie_link: phy@0 {
> > +		reg = <0>;
> > +		cdns,num-lanes = <1>;
> > +		#phy-cells = <0>;
> > +		cdns,phy-type = <PHY_TYPE_PCIE>;
> > +		resets = <&serdes_wiz1 1>;
> > +	};
> > +};
> > +
> > +&pcie0_rc {
> > +	status = "okay";
> 
> As much as I like these at the top, the new format rules seems to
> suggest "status" properties should go at the bottom of the node.

I failed to notice that. Thank you for pointing this out. I will fix
this in the v5 series.

[...]

Regards,
Siddharth.